FIFO

 

FIFO is needed when there are two different clock domains and we need to transmit the data. We must use FIFO when the fast sending data is to be delayed to match the speed of the receiver. We come across different cases let us understand one by one.

One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queuing element in the system, which is by common sense is required only when you slow at reading than the write operation.

        So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read. Depends on write rate and read rate).

        Statistically, Data rate varies in the system majorly depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration. (Statistics show that the data rate in the system Changes mainly depend on the load of the system. Therefore, in order to obtain a safe FIFO depth, we need to consider the worst case of data transmission across FIFOs during design).

         For worst case scenario, Difference between the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered. So in the question itself, data rate of read operation is specified by the number of idle cycles and for write operation, maximum data rate should be considered with no idle cycle.
         So for write operation, we need to know Data rate = Number of data * rate of clock. Writing side is the source and reading side becomes sink, data rate of reading side depends upon the writing side data rate and its own reading rate which is Frd/Idle_cycle_rd.

In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.

So following up with the equation as explained below: 

Fifo size = Size to be buffered = B-B * Frd/(Fwr* Idle_cycle _rd ).

That is, FIFO_DEPTH = Burst_length-Burst_length*rd_clk/(wr_clk*Idle_cycle_rd).

Here we have not considered the sychnronizing latency if Write and Read clocks are Asynchronous. Greater the Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.

 

Write clock : wr_clk; and in the write clock cycle, A data will be written into the FIFO every B clock cycle;

Read clock : r_clk; and in the read clock cycle, there will be X data read FIFO in every Y clock cycles.

Busrt_len for reading and writing : Same, both are Burst_len.What is the minimum depth required by the FIFO?

the amount of data written in a certain period of time (T) must be equal to the amount of data read, that is, A/B*wr_clk =X/Y*r_clk.

To calculate the maximum burst length burst_length of the written data, consider the worst case.

For example, if  80 data are written into the FIFO every 100 clocks, then in the case of back-to-back , burst_length=2*80=160.

If the data packet transmission method is clearly given in the question,

 For example, one package is far away from another package, that is, it does not affect each other, this back-to-back situation will not occur.

The minimum depth of the final FIFO: fifo_depth =Burst_length-Burst_len * X/Y * r_clk/w_clk

BTW: Usually, for safety's sake, more depth is left.

The derivation process of FIFO minimum depth calculation formula:

The core guidance is the conditions mentioned above: 

{ FIFO depth /(write rate - read rate)} >      { write data volume /write rate }

And in order to work under harsh conditions, we need to consider the situation when writing is the fastest and reading is the slowest:

            fifo_depth/[wda_width*(wr_clk-rd_clk*X/Y)]> Burst_len/wr_clk*rda_width

 Under normal circumstances, the bit width of read and write data is the same, there are:

            fifo_depth/(wr_clk-rd_clk*X/Y)> Burst_len/wr_clk

Sorted out: fifo_depth> Burst_len/wr_clk(wr_clk-rd_clk*X/Y)

           I.e. fifo_depth> Burst_len -Burst_len* (rd_clk/wr_clk)*X/Y

 

 If 100 write clock cycles can write 80 data, 10 clock cycles can read 8 data. Let wclk = rclk, consider back-to-back (20 clk sent data + 80clk sent data + 80clk sent data + 20clk no data, a total of 200 clk) to calculate the FIFO depth:

fifo_depth = 160-160*80%=160*128=32 .

If you let wclk=200Mhz, change to write 40 out of 100 wclk, rclk=100Mhz, read out 8 out of 10 r_clk. Then the minimum FIFO depth at this time should be:

fifo_depth = 80-80*

When reading and writing FIFO are not performed at the same time

  If the reading and writing of the FIFO are not performed at the same time, it is necessary to set the FIFO depth to the maximum burst number of write data .

Asynchronous FIFO minimum depth calculation example

Setting the depth of FIFO depends on the application scenario. 

Read and write FIFO used in SDRAM

     In SDRAM applications, setting the depth of a FIFO is generally sufficient to double the operation data . For example, SDRAM full page reads and writes 256, the corresponding depth is 512. Because the SDRAM read and write speed is definitely faster than the FIFO write speed, and the read speed of the subsequent FIFO, the overall rate of the SDRAM before and after the operation is the same.

Asynchronous clock data interface

     It is used for asynchronous clock domain data interface. If reading and writing are performed at the same time, the FIFO generally set is that the write clock is greater than the read clock. At this time, setting the depth of the FIFO must correspond to two clocks and write the largest burst data.

Assume that the write clock frequency is 40Mhz, the read clock is 25Mhz, and the maximum burst write data number at the write end is 100 data.
Then the depth is calculated as: 100-100*(2/40)=37.5, the corresponding depth is at least 38.

FIFO 

 An 8-bit wide AFIFO, the input clock is 100Mhz, the output clock is 95Mhz, a package is 4Kbit, and the sending distance between the two packages is large enough. Find the depth of AFIFO.

If it is large enough, it means that two adjacent transmissions will not affect each other, only one package needs to be considered;

Burst length calculation: if burst_length =4000/8=500, th 1Kbit=1024bit, so burst_length = 4*1024/8=512;

Calculation module fifo_depth = burst_length – burst_length*(X/Y)*(r_clk/w_clk)

Because the values ​​of X and Y are not given, all default to 1.

Get depth1=4000/8-(4000/8)*(95/100)=25.

Or depth =512-512*(95/100) = 25.6, so the minimum value of fifo_depth is 26

scenario can be two of following
Writing is faster than reading then there is possibility of overflow
Writing is slower than reading then there is possibility of underflow
In FIFO depth calculation we always have to consider worst case .Size of FIFO basically implies that how much data is required to buffer . And it is totally depend on data rate of reading and writing.
Data rate = Number of Data x Time Period
Difference = DRFAST – DRSLOW
Depth = Difference / Higher Freq. Time Period
Writing side is Source and Reading Side is Sink. If the data rate of writing is higher then the reading side’s data rate then the FIFO will now overflow.Another Type of depth calculation can be done by this method:
Consider F1 is writing frequency and F2 is reading frequency (F1>F2) and Data Size is D (Data Words)
Time taken to write to FIFO = DATA/F1
Data Read from the FIFO in the same time = (DATA/F1) xF2
Excess Data is FIFO (Backlog) = DATA-((DATA/F1) x F2
Read side will take more time to read the data so that time is called mop-up time.
Following is the calculation of mop-up time
Mop-up time = Backlog/F2 = DATA-(DATA/F1 F2)
Depth= Wmax – {Wmax x Fread x Wread}
Fwrite x WwriteFwrite = Clock Frequency of Write Clock Domain
Fread = Clock Frequency of Read Clock Domain
Wmax= Maximum number of worlds can be Written
Wwrite = Number of Writes in Per Clock
Wread = Number of reads in Per Clock
Following are some cases of FIFO depth calculation with perfect explanation.

Writing Side = 30 MHz => 33.33 ns Time Period
Reading Side = 40 MHz = > 25.0 ns Time Period



Consider the data size is = 10
Data Rate of Writing = 10 x (1/30) =333.33 ns
Data Rate of Reading = 10 x (1/40) =250.0 ns.
Difference between Data Rates = 333.33 – 250.0 = 83.33
Now divide with highest frequency time period = 83.33/25ns = 3.3332 = 4 (Aprox)
Depth of FIFO Should be 4



Writing Side = 80 Data/100 Clock = 100 MHz => 10ns Time Period
Reading Side = 80 Data/80 Clock = 80 MHz => 12.5ns Time Period
No Randomization



Data Size is = 80
Data Rate of Writing =80*10=800ns
Data Rate of Reading=80*12.5=1000ns
Difference = 1000-800=200ns
Now divide with highest frequency time period = 200/10ns=20
Depth of FIFO Should be 20



Writing Side = 10 MHz => 100 ns
Reading Side = 2.5 MHz=>400 ns
Word Size = 2



Data Rate of Writing =100*2=200ns
Data Rate of Reading=400*2=800ns
Difference = 800-200=600
Now Divide by the lowest frequency time period = 600/400 = 1.5 = 2
(Reading Frequency is slower than writing Frequency )



Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s)
Outgoing Data= 8 DATA/10 Clock

Above shows that the Writing Frequency is equal to reading frequency
20 Data + 80 Valid Data + 80 Valid Data + 20 Data

We will consider worst case

So we will consider 200 Cycles. In 200 Cycle 160 Data is written. it means 160 data continuously written in 160 clock it is the worst case .
At the reading side we will Read 8x16=128 data in 16x10=160 Clock Cycle.
So the Difference between Written Data and Read Back Data is = 160-128=32
FIFO Depth Should be 32

1.Calculate depth of an async fifo, but I am confused how to calculate it. The fifo parameters are as follows:

Write Clk Freq = 60 MHz.
Read Clk Freq = 100 MHz.
Maximum Write Burst Size = 1024.
Delay between writes in burst = 4 clk.
Read Delay = 2 clk.

2.A/D sampling rate is 50Mhz, dsp reading A/D rate is 40Mhz, or send 100,000 sampling data to DSP without loss, at least add a large capacity (depth) FIFO between A/D and DSP Just work?