EDA tools have been more stable for UPF 1.0 support, which is very important for product design
•Bottom-up hierarchy
flow is the only feasible approach in the era of billion gate SoC design
•Each block has its own UPF file
Easy to manage and reuse UPF file
Unified Power Format plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. UPF is intended to ease the job of specifying, simulating and verifying IC designs that have a number of power states and power islands. UPF is designed to reflect the power intent of a design at a relatively high level.
UPF scripts describe – Which power rails should be routed to individual blocks, when blocks are expected to be powered up or shut down how voltage levels should be shifted as signals cross from one power domain to another and if measures should be taken to retain register and memory-cell contents if the primary power supply to a domain is removed.
In reality, this comes at the cost of exponentially increasing leakage power. This is because the minimum gate-to-source voltage differential that is needed in CMOS devices to create a conducting path between the source and the drain terminals (known as threshold voltage) has been pushed to its limit. Leakage power is a function of the threshold voltage, and at smaller device geometries, its contribution to total energy dissipation becomes significant.
Device supply voltage and leakage current directly contribute to:
leakage power;
switching activity of the capacitive load on supply voltage ;
its switching frequency contribute to
dynamic power.
It is obvious that reducing supply voltage can be used to control both leakage and dynamic power dissipation. Mainstream power management and reduction techniques are solely based on direct manipulation of voltage, in terms of supply power connectivity and voltage area or power network distributions on the chip.
IEEE 1801-2015 is the latest version of the power-intent description standard for low-power VLSI design that started life as the Unified Power Format (UPF), and is sometimes referred to as UPF 2.1.
The
previous version, IEEE 1801-2009 was also known as UPF 2.0.
The
latest version of the standard incorporates elements of the Common Power Format
(CPF), which is managed by the Silicon Integration Initiative (Si2).
UPF Components
•
Power
Domain: – Groups of elements which share a common set of power supply
requirements
•
Power Supply Network – Abstract description of
power distribution (ports, nets, sets & switches)
•
Power State Table – The legal combinations of
states of each power domain
•
Isolation Strategies – How the interface to a
power domain should be isolated when its primary power supply is removed !
•
Retention
Strategies – What registered state in a power domain should be retained when
its primary power supply is removed !
•
Level
Shifter Strategies – How signals connecting power domains operating at
different voltages should be shifted !
Repeater
Strategies – How domain ports should be bufffered
Challenges in deploying UPF hierarchy flow in SoCs
UPF file becomes too big to manage in billion gate SoC era. The complexity of power state table (PST) increase almost exponential with the number of power domains. Some RTL coding styles are difficult or not compatible with UPF flow.Ø Custom design styles requires special attention in UPF flow.
UPF AND LOW POWER
1) Why do we need UPF?
2) What is the latest
version of vclp tool?
3) Why retention
register are used ?
4) What is A0 (always on
logic) or always on buffer ?
5) Why we use power
switch?
6) What is clamp value ?
7) What is static power
and dynamic power ?
8) For what reason we
control leakage power ?
9) what is isolation
strategy?
10) what is supply net ?
11) what is the flow of
UPF?
12) how many and mention
the types of retention register?
13) difference b/w vclp
v1.0 and vclp v2.0 and which is better?
14) what is level
shifter?
15) how many voltage
levels are there to define on and off state ?
16) what is the default
state in UPF?
17) what is the vclp
tool flow?
18) vclp tool is dynamic
power verification or static power verification?
19) what is clock gating
(CG) and power gating (PG) ?
20) what is freqency
scaling in upf ?
21)UPF vs CPF
22)UPF components
23)Challenges faced in
deploying UPF in SoC
24)Latest Version of the
tool used.Features
25)retention flop hardware
26)UPF command for the
power domain
27)Different types of
Always on logic
28)What is clock
gating?How do you use the same?Hardware.
29)What is power
gating?Hardware.
30)Power reduction
techniques.
31)Advanced low power
techniques.
32)What is crow bar
current?causes
33)Different types of
level shifter.
34)Different UPF
commands.
35)What does set_scope
does?
36)UPF for power system
table.
37)steps for the
environment setup for the upf
38)where are all you
declare upf in the RTL To GDS2 flow
39)steps to reduce the
compile in UPF
40) What is PUT?
41)Why do we need PUT?
42)Who should deliver
PUT?
43)How does communication between library design and SoC designer is important to
make UPF compliant library at what
conditions?
44)Write upf for buffer insertion.
45)UPF for the hierarchy flow.
46)Write UPF for the SoC.
47)Low power techniques for SoC
48)What is the benefit of smaller power switch and bigger power switch?
49)How do you place the switch?
50)DFT implications in low power?
51)Power gating considerations
52)Power gating flow
53)Parameters captured in full power gating results.
54) Parameters captured in selective power gating results.
55)Power aware design flow.
56) Library Requirements for LPD.
57)Memory retention methods
58)Single control live slave hardware and working
59)Dual control baloon and single control baloon
60)Reduced VDD retention
61) Diode Biasing
62)Source Biasing
63)Difference between the GUPF file and the UPF file.
64)Different strategies for low power.
65)Environment setting of the tool for UPF/CPF.
66)Low power coverage methodology?
67)What is incrementality elaboration?
68)Integration
of low power UPF into the SoC?
69)set_repeater and set_port_attributes.
70)rtl optimization for the low power?
71)Logic optimization for low power?
72)Layout optimization for low power?
73)What is zero idle power?
74)Power management bugs.How to resolve?
75)What is clamp value 0 and clamp value1?
76)Tool didn’t understand the port connection defined in RTL through UPF.How to resolve?
77)X value doesnot exist in emulation how to highlight OFF power domain?
78)Power sequence failure in hard macros?
79)Hard macros interface corruption?
80)How to corrupt an array which lise in multivoltage domain?
81)What is meant by power down and power up sequence in SoC?
82)UPF 2.0 migration issues?How to resolve it?
83)Different types of low power checks.explain
