DIGITAL LOGIC
Digital logic questions are mainly from the
below topics:
Basics of Digital Design
Deign all gates using MUX.
MUX using buffers.
Gate conversion.
XOR vs XNOR –special characteristics.
Buffer vs Inverter.
Different kind of Buffers.
Latch vs Flip Flops.
Dff to Tff conversion .
JK vs RS ff.(RAQ)
Master slave flops/ edge triggers flops.
Truth tables of flops should be on tips for all quick answers.(RAQ)
Flip flop parameters like setup/hold/clock2q delay, propagation delay of
cells/fanout/fanin.
Multiplier and divider circuitry implementation and logical implementation of
any number of multiplier and divider.
Different type of adders.
Mod N counter/Frequency Dividers.
Sequence detector FSM design.
Design a FSM to detect input stream is divisible by x(any number) or not.
Glitch Jitter skew.
Edge detection circuitry.
Ripple Johnson counter.(RAQ)
Linear Feedback Shift Registers.(RAQ)
Question is usually asking to convert 14 (or some other small number) from
decimal to binary, hex, and octal representations.
Knowledge about:
Digital cicruits in general, boolean logic.
Analog design interfacing with digital logic and with quite some digital logic
inside.
Firmware and embedded processor knowledge, including embedded OS.
Silicon validation work and PCB knowledge (design and/or bringup of new board).
Test, packaging, yield, foundry experience.
VHDL: difference between signals and variables.
Clock domain crossing (verilog and VHDL).
Combinational vs sequential logic.
Inference versus instantiation.
What
are some common design/scenarios for verification given during a design
verification interview?
This can
vary based on your experience, background, your domain of expertise etc.
An
interviewer can make up a design based on your experience level. The complexity
and detailed design specifications can be varied. Questions can also vary from
asking for basic verification scenarios to designing test benches, specific
corner cases, debugging approaches, writing code for stimulus, checkers or
other components etc.
The goal
is to see how well candidate thinks through and understands the
concepts/solutions.
Following
are some :
1. Simple
Sync/Async FIFOs
2. A
simple ALU (Arithmetic Logic Unit). For an entry engineer, I can ask to verify
same as a black box with just 3 instructions. For some one experienced, I can
make it complex with making it superscalar, pipelining etc.
3. A
DMA controller - Can be a simple single channel DMA or make it complex with
more details like multiple parallel channels, arbitration, peripheral agents
etc and ask
4. A
packet switch/router - Can be a simple two port switch for an entry engineer or
a multi port/multi speed switch/router with queuing/flowcontrol and more
specific details.
5. A
master/slave agent on a shared bus - Could be a simple generic one or more
specific with AXI or similar protocol agents.
6. Simple
SRAM/DRAM memories, single port / multi port , different speeds
7. Different
types of adders, transceivers, arbiters, state machines, sequence detectors etc
8. Cache
memories and controllers
9. Interrupt
controllers
The
complexity will depend on number of factors like following (a sample list)
1. Number
of processing agents, caching agents, I/O agents in the coherence domain
2. Type
of Coherence protocol - snooping vs directory, supported coherence states (M,
E, S, I, O, F), snoop filtering support etc
3. Hierarchy
of caches as inclusive/exclusiveness of caches
4. Invalidation/Eviction/Writeback
policies
The main
goal for verification is to ensure that all caches are coherent at any given
point in time. In most of my experience in verifying coherency, I have used
constrained random stimulus along with a collection of checkers and coverage to
ensure correctness and completeness
For a
constrained random stimulus, you randomize all the request types originating
from all agents, various address patterns (shared vs new vs conflicting etc), various
message delays etc. The coherency checker can then look at order of requests
across the coherence domain and predict the states and completeness of
requests.
In
addition, based on the micro architectural implementation, there might be need
to create several other constrained/focused scenarios - eg. back pressure on
request/snoop/data message channels, credit based controls if any etc
Questions on timing analysis, Verilog HDL, logic design, Sequential and
combination circuits, finite state machine, synthesis, verification and
testing, JTAG, etc. questions on routing congestion and area reduction,
standard cells and macros.Apart from these, Memories, ADC, DAC, PLL are a few
circuits on which you may face questions. Know how the fabrication of the IC is
done step-by-step.
The
process of turning bare silicon wafer into a packaged IC (diffusion, implant,
lift-off, photo-resist, lithography, rca cleaning, metalization, dopant,
silicide gate structure, etc)
=>VLSI design rules that involves :
Metal spacing/width,stick diagrams etc.=>in depth knowledge of
CMOS:parasitics,channel length modulation,miniaturization etc.
As a VLSI engineer, you need to know few commands of Linux command line
that makes your job easier.
Here are the topics which need to learn:
1.
Basic Linux commands
2.
Using wildcards
3.
Seeking help
4.
File handling
5.
Composite commands
6.
Users and permissions
7.
Basic scripting
8.
Environment variables
9.
Text editor
Digital design (many topics
within digital design), CMOS circuit design & underlying concepts (sizing,
chain of inverters, logical effort, combinational & sequential logic
design, drive strength, power considerations & repercussions , derating for
PVT…) , FPGA’s , Board related concepts , HDL coding (Systemverilog , Verilog ,
VHDL), Good HDL coding practices, Synthesis concepts, ASIC design concepts,
Verification methodologies, Basic serial communication protocols & their
concepts, Basic & Advanced bus theory & knowledge of prominent bus
protocols (AMBA - APB / AHB / AXI … ). Working level knowledge of a particular
protocol or domain - storage (SSD’s / SATA ) / communication (Ethernet / USB …)
/ Memory interfaces / DSP knowledge .
Knowledge of computer
architecture (many sub-topics within this topic) is central to all concepts involved
as everything is connected to a processor core.
Good working level knowledge
of Verification methodologies - UVM / OVM.These are just technical skills,
besides these, you need to know how to use tools and hands on with Unix
environment / scripting for automation of tasks.Have out your study plan
and start with basics & ask a senior manager / colleague in the domain of
your interest to mentor / guide you with your career plan.
Experienced Engineer in
VLSI FRONT END, need to know the Static Timing Analysis, Clock Domain
Crossing,Linting,Power,Assertions and verification concepts.DFT understanding
is added advantage.
Design For Testability (DFT) covers all test-ability of chip
and manufacturing defects testing.Combine to DFT, we have DFX where we
include for Testablity. Being DFT engineer, person should
have knowledge of Scan insertion/stitching,Automatic Test Pattern
Generation(ATPG),Built in self test(BIST): Logical BIST, Memory
BIST,Programmable MBIST.Automatic Test Equipment(ATE).In depth knowledge of
Memories. In market DFT, also have its own recognition separately.
DFD:Design for Debug DFM :Design for Manufacturing DFS : Design for
Security.
DFV:Design for validation ,Design for Reliability.
For DV ,it is growing , and it will continue to grow , the reason
behind is quality of the product delivered from INDIA , trust towards Indian
Hardware engineer. Google India has started hiring DV engineer is indication of
it.Most UVM(System verilog framework) users are from India.In coming days ,
India will have significant contributions towards DV
community.
At experience level people must have good knowledge of
Methodologies like UVM/OVM, then One must must know Gate level Simulation(GLS).
Another thing comes for a verification engineer is high speed protocols. as day
by day designs are more faster and small sized, these are also
required for a Designer.
FPGA PRIMITIVES:MMCM,GTH/GTX,SERDES,Iddr,oddr,Idelay,Odelay
FPGA EMULATION:ARCHITECTURE ,
LUTS,CLBS,BRAM,DISTRIBUTED RAM,CLOCK BUFFER AND CLK RESOURCES, FPGA
P AND R,ROUTING,CONGESTION,TIMING-CREATE/GEN CLK,INPUT/OUTPUT
DELAY,MAX DELAY,MCP,FALSE PATH,DESIGN:SINGLE PORT.DUAL
PORT,RAMS,FIFO,SERDES ETC,DDR/PCI,
FPGA PRIMITIVES:MMCM,GTH/GTX,SERDES,Iddr,oddr,Idelay,Odelay
Partitioning and design implement for multi fpga
system,Multicore,multi clocks experience,SHELL,Dpi,pli,Vimeditor,c based
transaction tb,in circuit emulation,clocking scenarios in emulation
Physical Design
Backend where it involves Physical
design(MAP, FLOOR PLAN, ROUTING, LAYOUT).experienced Engineer in VLSI FRONT
END, need to know the Static Timing Analysis, Clock Domain
Crossing,Linting,Power,Assertions and verification concepts.DFT understanding
is added advantage.
In market DFT, also have its own recognition separately.
Design For Testability (DFT) covers all test-ability of
chip and manufacturing defects testing.Combine to DFT, we have DFX where we
include for
Testablity. Being
DFT engineer, person should have knowledge of Scan
insertion/stitching,Automatic Test Pattern Generation(ATPG),Built in self
test(BIST): Logical BIST, Memory BIST,Programmable MBIST.Automatic Test
Equipment(ATE).In depth knowledge of Memories.
DFD:Design for Debug DFM :Design for Manufacturing DFS : Design for Security.
DFV:Design for validation ,Design for Reliability.
For DV ,it is growing , and it will continue to grow , the reason behind
is quality of the product delivered from INDIA , trust towards Indian Hardware
engineer.
An experienced designer should have very good understanding of
Fabrication lab requirement, which involve all Design rules
check(DRC),Layout vs Schematic (LVS),all PVT stuffs, On chip variations,
Parasitic exchange formats(SPEF/SDF). If for Verification,
very good understanding of SV(system verilog), sometime SystemC(depends on JOB
requirement), Assertions, UVM basics.At experience level people must have good
knowledge of Methodologies like UVM/OVM, then One must must know Gate level
Simulation(GLS). Another thing comes for a verification
engineer is high speed protocols. as day by day designs are more faster and
small sized, these are also required for a Designer.
Physical Design
Backend where it involves Physical design(MAP, FLOOR PLAN, ROUTING, LAYOUT)
To be a good verification engineer
you have to know some on each stage of ASIC flow.
ASIC verification has
many sub-levels of verification concern
· Functionality
and how the DUT (Design Under Test) will react to different stimulus.
· Timing
and whether the DUT will violate the timing constraints put by the design
specs.
· Physical
Verification on the final transistor layout
Test
Bench module will be implemented in behaviour model to check the RTL.
Design module will be implemented in RTL which usually will be used in the
ASIC/FPGA Flow. Which is very basic input in the ASIC/FPGA flow.But in order to
implement RTL, will be using only synthesizable code which means, any kind of
synthesizable tool(usually design_compiler(synopsys), Genus(cadence),..) can
understand and able to generate Gate level netlist for the next flow in the
ASIC/FPGA Flow.
A RTL will be checked through with below tools
linting checks - checks for synthesizable code is been implemented.
clock domain crossing checks - checks for synchronizers were implemented
correctly in case different clock domains were used in design module.
synthesis - checks the timing constraints were meeting.
Along with functional verification & above tools will be used to check RTL
ASIC
RTL interview questions are from
Respective Projects
Design,Microarchitecture
Timing closure
Low power if any
STA
CDC
Linting
perl/python/tcl
Verification
SV added plus
Timing closure:
·
what are the parameters that cause my design to fail timing
closure?
·
What can I fix before trashing the design or change it
completely?
·
What are the implications with adding a register in the critical
path and what are the best practice to re-sync the pipeline after adding any
number of registers?
·
What is the relationship between the clock skew, the clock path,
the clock uncertainty?
·
Does it affect my pipeline stages if retiming is activated by
default?
"Outside" interface:
·
What extra-caution measures should I take when using an external
clock?
·
How can I be sure to sample an external async signal?
·
How do I constrain external signals based on the board
properties?
·
How to sample a multibit external digital signal?
Clock domain crossing:
·
How to mitigate the problem?
·
What is MTBF? Any example?
Program 1: AND
Gate
module gate_and(a,b,
c);
input a,b;
output c;
reg c;
always @ (a,b)
begin
c <= a & b;
end
endmodule
Program 2: OR
Gate
module gate_or(a,b,
c);
input a,b;
output c;
reg c;
always @ (a,b)
begin
c <= a || b;
end
endmodule
Program 3: NOT Gate
module gate_not(a,b);
input a;
output b;
reg b;
always @ (a)
begin
b <= ~a;
end
endmodule
Program 4: NAND Gate
module gate_nand(a,b,
c);
input a,b;
output c;
reg c;
always @ (a,b)
begin
c <= ~(a & b);
end
endmodule
Program 5: NOR Gate
module gate_nor(a,b,c);
input a,b;
output c;
reg c;
always @ (a,b)
begin
c<=~(a || b);
end
endmodule
Program 6:XOR Gate
module gate_xor(a,b,c);
input a,b;
output c;
reg c;
always @ (a,b)
begin
c<=(a^b);
end
endmodule
Program 7:XNOR Gate
module gate_xor(a,b,c);
input a,b;
output c;
reg c;
always @ (a,b)
begin
c<=~(a^b);
end
endmodule
Program 8:HALF ADDER
module h_add(a,b, sum,carry);
input a,b;
output sum,carry;
reg sum,carry;
always @ (a,b)
begin
sum<=(a^b);
carry<= (a&b);
end
endmodule
Program 9:FULL ADDER
module h_add(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
reg sum,carry;
always @ (a,b,cin)
begin
sum<=(a^b^cin);
carry<= (a&b)||(b&cin)||(a&cin);
end
endmodule
Program 10: D-LATCH WITH A POSITIVE GATE
module latch (g, d, q);
input g, d;
output q;
reg q;
always @(g or d)
begin
if
(g)
q
<= d;
end
endmodule
Program 11:D-LATCH
WITH A POSITIVE GATE AND AN ASYNCHRONOUS CLEAR
module latch (g, d,
clr, q);
input g, d, clr;
output q;
reg q;
always @(g or d or
clr)
begin
if (clr)
q <= 1'b0;
else if (g)
q <= d;
end
endmodule
Program 12: 4-BIT
LATCH WITH AN INVERTED GATE AND ASYNCHRONOUS PRESET
module latch (g, d, pre, q);
input g, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always @(g or d or
pre)
begin
if (pre)
q <= 4'b1111;
else if (~g)
q <= d;
end
endmodule
Program 13:D-FLIP FLOP
WITH NEGATIVE EDGE CLOK AND ASYNCRHONOUS CLEAR
module flop(clk, d,
clr, q);
input clk, d, clr;
output q;
reg q;
always @(negedge clk
or posedge clr)
begin
if (clr)
q <= 1'b0;
else
q <= d;
end
endmodule
Program 14:D-FLIP FLOP
WITH POSITIVE EDGE CLOK AND SYNCRHONOUS SET
module flop (clk, d, s, q);
input clk, d, s;
output q;
reg q;
always @(posedge clk)
begin
if (s)
q <= 1'b1;
else
q <= d;
end
endmodule
Program 15:D-FLIP FLOP
WITH POSITIVE EDGE CLOK AND CLOCK ENABLE
module flop (clk, d,
ce, q);
input clk, d, ce;
output q;
reg q;
always @(posedge clk)
begin
if
(ce)
q <=
d;
end
endmodule
Program 16: 4-BIT
REGISTER WITH A POSITIVE EDGE CLOCK, SYNCHRONOUS SET AND CLOCK ENABLE
module flop (clk, d, ce, pre, q);
input clk, ce, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always @(posedge clk
or posedge pre)
begin
if
(pre)
q <= 4'b1111;
else if (ce)
q <=
d;
end
endmodule
Program
17: TRI-STATE BUFFER
module three_st (t, i, o);
input t, i;
output o;
reg o;
always @(t or i)
begin
if (~t)
o = i;
else
o = 1'bZ;
end
endmodule
Program 18:TRI-STATE
BUFFER USING CONDITIONAL OPERATORS (USING CONCURRENT ASSIGNMENTS)
module three_st (t, i, o);
input t, i;
output o;
assign o = (~t) ? i:
1'bZ;
endmodule
Program 19: 4-BIT
UNSIGNED UP COUNTER WITH ASYNCHRONUOS CLEAR
module counter (clk, clr, q);
input clk, clr;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk
or posedge clr)
begin
if (clr)
tmp <= 4'b0000;
else
tmp <= tmp + 1'b1;
end
assign q
= tmp;
endmodule
Program 20: 4-BIT
UNSIGNED DOWN COUNTER WITH SYNCHRONUOS SET
module counter (clk,
s, q);
input clk, s;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 4'b1111;
else
tmp <= tmp - 1'b1;
end
assign q = tmp;
endmodule
Program 21: 4-BIT
UNSIGNED UP COUNTER WITH AN ASYNCHRONOUS LOAD FROM THE PRIMARY INPUT.
module counter (clk,
load, d, q);
input clk, load;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk
or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= tmp + 1'b1;
end
assign q = tmp;
endmodule
Program 22: 4-BIT
UNSIGNED UP COUNTER WITH A SYNCHRONOUS LOAD WITH A CONSTANT.
module counter (clk,
sload, q);
input clk,
sload;
output
[3:0] q;
reg [3:0]
tmp;
always @(posedge clk)
begin
if
(sload)
tmp
<= 4'b1010;
else
tmp
<= tmp + 1'b1;
end
assign q = tmp;
endmodule
Program 23: 4-BIT
UNSIGNED UP COUNTER WITH AN ASYNCHRONOUS CLEAR AND A CLOCK ENABLE.
module counter
(clk, clr, ce, q);
input clk,
clr, ce;
output
[3:0] q;
reg [3:0]
tmp;
always @(posedge clk
or posedge clr)
begin
if
(clr)
tmp
<= 4'b0000;
else
if (ce)
tmp
<= tmp + 1'b1;
end
assign q = tmp;
endmodule
program 24: 4-BIT
UNSIGNED UP/DOWN COUNTER WITH AN ASYNCHRONOUS CLEAR.
module counter (clk,
clr, up_down, q);
input clk,
clr, up_down;
output
[3:0] q;
reg [3:0]
tmp;
always @(posedge clk
or posedge clr)
begin
if
(clr)
tmp
<= 4'b0000;
else
if (up_down)
tmp
<= tmp + 1'b1;
else
tmp
<= tmp - 1'b1;
end
assign q = tmp;
endmodule
Program 25: 4-BIT SIGNED
UP COUNTER WITH AN ASYNCHRONOUS RESET.
module counter (clk,
clr, q);
input
clk, clr;
output
signed [3:0] q;
reg signed
[3:0] tmp;
always @ (posedge clk
or posedge clr)
begin
if
(clr)
tmp
<= 4'b0000;
else
tmp
<= tmp + 1'b1;
end
assign q = tmp;
endmodule
Program 26: 4-BIT
SIGNED UP COUNTER WITH AN ASYNCHRONOUS RESET AND A MODULO MAXIMUM.
module counter (clk,
clr, q);
parameter MAX_SQRT =
4, MAX = (MAX_SQRT*MAX_SQRT);
input
clk, clr;
output
[MAX_SQRT-1:0] q;
reg [MAX_SQRT-1:0]
cnt;
always @ (posedge clk
or posedge clr)
begin
if (clr)
cnt
<= 0;
else
cnt
<= (cnt + 1) %MAX;
end
assign
q = cnt;
endmodule
Program 27: 4-BIT
UNSIGNED UP ACCUMULATOR WITH AN ASYNCHRONOUS CLEAR.
module accum (clk,
clr, d, q);
input clk,
clr;
input [3:0]
d;
output
[3:0] q;
reg [3:0]
tmp;
always @(posedge clk
or posedge clr)
begin
if
(clr)
tmp
<= 4'b0000;
else
tmp
<= tmp + d;
end
assign q = tmp;
endmodule
Program 28: 8-BIT
SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, SERIAL IN AND SERIAL OUT.
module shift (clk, si,
so);
input clk,si;
output
so;
reg [7:0]
tmp;
always
@(posedge clk)
begin
tmp <=
tmp << 1;
tmp[0]
<= si;
end
assign so = tmp[7];
endmodule
Program 29: 8-BIT
SHIFT-LEFT REGISTER WITH A NEGATIVE-EDGE CLOCK, A CLOCK ENABLE, A SERIAL IN AND
A SERIAL OUT.
module shift (clk, ce,
si, so);
input clk,
si, ce;
output so;
reg [7:0]
tmp;
always @(negedge clk)
begin
if
(ce) begin
tmp <=
tmp << 1;
tmp[0]
<= si;
end
end
assign so = tmp[7];
endmodule
Program 30: 8-BIT SHIFT-LEFT REGISTER WITH A
POSITIVE-EDGE CLOCK, ASYNCHRONOUS CLEAR, SERIAL IN AND SERIAL OUT.
module shift (clk,
clr, si, so);
input clk,
si, clr;
output so;
reg [7:0]
tmp;
always @(posedge clk
or posedge clr)
begin
if
(clr)
tmp
<= 8'b00000000;
else
tmp
<= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule
Program 31: 8-BIT
SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, A SYNCHRONOUS SET, A SERIAL IN
AND A SERIAL OUT.
module shift (clk, s,
si, so);
input clk,
si, s;
output so;
reg [7:0]
tmp;
always @(posedge clk)
begin
if
(s)
tmp
<= 8'b11111111;
else
tmp
<= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule
Program 32: 8-BIT
SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, A SERIAL IN AND A PARALLEL OUT.
module shift
(clk, si, po);
input clk,
si;
output
[7:0] po;
reg [7:0]
tmp;
always @(posedge clk)
begin
tmp
<= {tmp[6:0], si};
end
assign po = tmp;
endmodule
Program 33: 8-BIT
SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, AN ASYNCHRONOUS PARALLEL LOAD,
A SERIAL IN AND A SERIAL OUT.
module shift
(clk, load, si, d, so);
input clk,
si, load;
input [7:0]
d;
output
so;
reg [7:0]
tmp;
always @(posedge clk
or posedge load)
begin
if
(load)
tmp <= d;
else
tmp
<= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule
Program 34: 8-BIT
SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, A SYNCHRONOUS PARALLEL LOAD, A
SERIAL IN AND A SERIAL OUT.
module shift (clk,
sload, si, d, so);
input clk,
si, sload;
input [7:0]
d;
output so;
reg [7:0]
tmp;
always @(posedge clk)
begin
if
(sload)
tmp
<= d;
else
tmp
<= {tmp[6:0], si};
end
assign so
= tmp[7];
endmodule
Program 35: 8-BIT
SHIFT-LEFT/SHIFT-RIGHT REGISTER WITH A POSITIVE-EDGE CLOCK, A SERIAL IN AND A
SERIAL OUT.
module shift (clk, si,
left_right, po);
input clk,
si, left_right;
output po;
reg [7:0]
tmp;
always @(posedge clk)
begin
if
(left_right == 1'b0)
tmp
<= {tmp[6:0], si};
else
tmp
<= {si, tmp[7:1]};
end
assign po = tmp;
endmodule
module ASK_modulator(clk,rst,din,dout);
input clk,rst;
input din;
output dout;
wire dout;
reg cnt;
reg carrier;
always @(posedge clk)
begin
if(!rst)
begin
cnt<=2'b00;
carrier<=0;
end
else
if(cnt==1)
begin
cnt<=0;
carrier<=~carrier;
end
else
begin
cnt<=cnt+1;
carrier<=carrier;
end
end
assign dout=din&carrier;
endmodule
module ASK_demodulator(clk,rst,ddin,ddout);input clk,rst;input ddin;output ddout; reg ddout;reg [4:0]cnt1;reg [2:0]cnt2; always @(posedge clk)begin if(!rst) cnt1<=5'b00000; else if(cnt1==5'b10011) cnt1<=5'b00000; else cnt1<=cnt1+1;end always @(posedge ddin)begin if(!rst) cnt2<=3'b000; else cnt2<=cnt2+1;end always @(posedge clk)begin if(cnt1==5'b00000) begin if(cnt2>1) ddout<=1; else ddout<=0; cnt2<=3'b000; endend
endmodule Design
the 4:1 multiplexer circuit using TG switches.
Design a 4:1 mux using three 2:1 TG multiplexers.
Consider the 2-input XOR function.
What is the practical application of XOR
and XNOR gate?
A particular circuit could be given and
asked to find the output.
Combinational Circuits:-Implement all the basic gates using 2:1 Mux.
NAND vs NOR circuitry.
Circuit for 1st one
finder for a series input
For an input clk of f frequency generate an output of 2*f frequency
For an input clk of f frequency generate a clk output of frequency f÷(3/2) or
(5/2)
Clock dividers with 50℅ duty cycle
Sequence detectors
Output should be high for only odd +ve edge transition
Max frequency calculation with transmitter as +ve edge flip flop and receiver
as - ve edge flipflop with combinational circuits having false paths in it
Sync and Asynchronous counters (Mod n
counter)
Mealy,Moore
Synchronous and Async Reset difference
Latch vs Flipflop
All logic gates implementation using NAND , NOR
Logic gate implementation using MUX .
Boolean exp implementation using Decoder.
No. of 2*1 mux needed for 64*1 mux
No. of 2*4 decoders needed to implement 4*16 Decoder
Implement
4:1 Mux using 2:1 Mux
Implement
Full adder using 4:1 Mux
A function will be given like f(a,b,c) = sum(m){1,3,5,6} and implement it using 4:1 and 2:1 Mux.
Implement 2:1 Mux using Tristate buffers.
Design 4:16 Decoder using 3:8 Decoder.
Design Full adder using 3:8 Decoder.
Implement Full adder(FA),HA,FS,HS using either NAND or NOR gates.
Implement Full adder using Half Adder.
LAC adder and it's working principle.
Questions on Implicants,Prime Implicants and Essential Prime Implicants.
Karnaugh Map and Tabulation Method - Which one to use and when.
4 x 4 Mux
8 bit counter
Decade Counter
32 x 8 ROM
32 x 8 RAM
32 x 8 FIFO
1) Design a 4 bit combinational circuit 2’s complementer. The output generates the 2’s complement of the input binary number.Show that the circuit can be constructed using exclusive NOR gates.
2) Design a code converter that converts decimal
digits from 842 code to BCD.
3) Design a combinational circuit that converts a 4
bit Gray code to 4 bit number.Implement using exclusive NOR gates.
4) Implement with a mux
a)F(A,B,C,D)=∑m(0,1,3,4,8,9,15)
b)F1(A,B,C,D)=∑m(1,3,4,11,12,13,14,15)
c)F2(A,B,C,D)=∑m(1,2,5,7,8,10,11,13,15)
5) a)Draw the logic
diagram of 2-4 decoder using a)NOR gates b)
NAND gates b) Construct 4-16 decoder with four 3 to 8 decoder.
1)Convert RS FF to
JK FF
2) A counter that
follows the sequence 1,2,3,12,3…Design a state machine to follow this sequence
using D type FF and as few gates.
3) Convert DFF to TFF
4) Draw a gated latch.
Give two ways of
converting a two input NAND gate to an inverter.
Hazards
types and Causes.
Sequential
Circuits:-
Conversion
of one Flip Flop to another like JK to SR,T to D,etc.
Race around condition in JK flip flop and how to avoid it.
Difference between Latch and Flip Flop.
Different types of shift register and it's working.Timing diagram
Difference between Johnson and Ring Counter.Timing diagram
Design a synchronous counter using JK flip flop and count sequence in XS-3
code.
Implement a counter with Mux
Design a MOD 10 counter with 50%/33% duty cycle.
Difference between Mealy and Moore State Machine.
Sequence detector problems like Design a Mealy/Moore FSM for 1001.
Design a Mealy FSM for 010 and 1010.
Frequency Divider Circuits.
Design an XOR gate using a 4:1 mux. Modify the circuit in a) to produce a 2-input XNOR
Design a CMOS logic gate for the function f= a.b+a.c+b.d
Design a NAND3 gate using an 8:1 mux
Design a NOR3 gate using an 8:1 mux as a basis.
Why Race Condition?
Q
: If inverted op of D ff is connected to input of ff how the flop behave ??
A
: It behave as T flipflop
Q : Design a circuit for dividing input frequency by 2 ?
A
: please give input frequency as the clock of T flip flop & input of flop
is 1. Output will be input clock divide by 2 .
Q : What are the different type of adder implementation ?
A : Carry Ahead,And & Xor combinational circuit , Ripple carry .
Q: Give the Truth Table for a Half Adder ?? Give gate level Implementaion of it
??
A:
A B Y Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Y = A xor B , Carry = A and B
Q : Design OR gate from 2:1 mux
A
: assume that A & B are the input of OR gate . Then
Give A as sel pin of 2:1 mux , B to the 0th pin Mux & 1 to 1th pin of Mux
Q : Design a D FF from two latches ?
A
: Connect two latches serially , First latch enable pin positive level &
second latch enable pin
as negative level or vice versa . Connect clock to enable pin it will work as
FF .
Is the design area efficient? Will it cause problems in layout? Can we reduce the power Consumed? Is it easy to test post silicon ? Is it easy to verify?
What are different type of counters?
Ans: ripple counter, synchronous counter, ring counter, Johnson counter etc.
Which counter will consume less power? Which will have largest area?
Another thing is to ask to design a logic circuit.
For instance, given an input digital clock design digital circuit to divide the
clock by 3, how about divide by 5?
Design a circuit to
divide a clk by 2 ,4 , 8 ?
Design a counter for a simple given sequence
(0,1,3,2)
Mealy and Moore FSMs.
How to compare two input
bit streams.
SOP-POS(SUM OF PRODUCT -
PRODUCT OF SUM) form conversion of digital equations and logic
optimization
Implementing functions using Decoder/Encoder
Waveform deterioration
Mathematics equations
design and optimized hardware
Memory design questions
Race conditions in
Digital circuitry
How many 2:1 Muxs are
needed for 8:1/16:1 Mux.
Implementation of MUX
using Tristate BUFFERS.
Area calculations of Mux
implementation from different ways i.e. whic MUX will have more area on chip
8:1 MUX, 8:1 Mux using 2:1 Mux.
HALF-ADDER ←> FULL ADDER conversion
RAS CAS in SRAM.
SRAM cells explanations working.
Ram vs FIFO.
SIPO/PISO related logic for fast implementations of any given problem
How to do Handshake between designs.
Disk rotation detection/Ant walking and other probability
questions, expected to be answered as digital design concept.
What is metastability?
When setup or hold
window is violated in an flip flop then signal attains a unpredictable value or
state known as metastability.
What is MTBF? What it
signifies?
MTBF-Mean Time Before
Failure
Average time to next
failure
How chance of metastable
state failure can be reduced?
Lowering clock
frequency
Lowering data
speed
Using faster flip flop
What are the advantages
of using synchronous reset ?
No metastability
problem with synchronous reset (provided recovery and removal time for reset is
taken care).
Simulation of
synchronous reset is easy.
What are the
disadvantages of using synchronous reset ?
Synchronous reset
is slow.
Implementation of
synchronous reset requires more number of gates compared to asynchronous reset
design.
An active clock is
essential for a synchronous reset design. Hence you can expect more power
consumption
What are the advantages
of using asynchronous reset ?
Implementation of
asynchronous reset requires less number of gates compared to synchronous reset
design.
Asynchronous reset is
fast.
Clocking scheme is
not necessary for an asynchronous design. Hence design consumes less power.
Asynchronous design style is also one of the latest design options to achieve
low power. Design community is scrathing their head over asynchronous design
possibilities.
What are the disadvantages
of using asynchronous reset ?
Metastability
problems are main concerns of asynchronous reset scheme (design).
Static timing analysis
and DFT becomes difficult due to asynchronous reset.
In a system with
insufficient hold time, will slowing down the clock frequency help?
No.
Making data path
slower can help hold time but it may result in setup violation.
In a system with
insufficient setup time, will slowing down the clock frequency help?
Yes.
Making data path
faster can also help setup time but it may result in hold violation.
Setup
and Hold time and what is Meta-stability and how to avoid it?
Setup and hold time of
flops and what it signify and what is its violations.
What are set up time & hold time
constraints? What do they signify? Which one is critical for estimating maximum
clock frequency of a circuit?
Setup and hold time
definition and expression for both latch and flipflop
Setup time and Hold time
- (i)Given a simple flop-flop design, find the maximum frequency of
operation?
Explain
hold time/occurrence of hold violation.
Clock Skew/Slew/Slack/Propagation Delay.
What are False Path and Multicycle Path.?
Hold Slack Calculation of a given Circuit.
Frequency calculation of a given Circuit.
Reset Strategies and what is asynchronous assertion and Synchronous
Deassertion.
Clock domain Crossing and what is asynchronous CDC.
What are synchronizers and when to use them?
FIFO depth Calculation of a Asynchronous FIFO. How to calculate depth of FIFO for rate change implementation ?
FIFO wrapper. Diagram of FIFO
What is Empty and Full Condition in FIFO.
Between Binary and Gray Counter, which one to use and why?
Meta stability.
Operating frequency
calculations.
FIFO depth calculation.
Data accumulation (FIFO, read-ahead FIFO, etc)
Priority encoding
Arbitration (round-robin, weighted round-robin, etc)
Data window inspection, shifting, wrapping
Data width transitions
If there are 4 inputs in decoder..no of output lines?
Application of
decoder.
. Signal vs variable
. Fsm types..
difference between the two with block diagram
. No of inputs in 4
bit parallel adder
Full adder
Buffer using XNOR
Setup and hold
time.
If a number 101 is
left shifted 2 times, what is the value of new number in decimal system. Ans.
20 (10100)
Difference between flip flops and latch
Libraries used in
vhdl...why ieee.std_logic library is used?
Verilog 2001 vs 95
Latches
clock gatimg
resource sharing
operator overloading
operator balancing
power gatimg
flip flop vs latches
counters
registers
memories
fifo
fifo depth
meta stability resolve of it
overlap
skew
slack
setup
hold fix ‘
encoder
decoder
throughput latency calculation
bufg
power reduction in rtl
Fsm verilog mealy
moore
Clock schemes
pattern gen
defparam
local parameter
parameter
dynamic ram sram and
its types.memory calculation
.shift register types
.all digital mux encoder flip conversions race race around glitches static
hazard and dynamic hazards
1010 11001 overlap or
non overlap
Booth multiplier
verilog
Full subt adder carry
Mealy conversion to
moore.
Booth encoding
For loop generate
while loop forever
: Encoding schemes
.clocking schemes. Advantages
Save adder
Verilog rtl synthesis
Task and functions
Mcp false path sta dta
: Generate statements
for multiplication
Parity error check and
correction clock crossing in verilog verilog renerta web and tidbits fully
Setup and pulse width
Implement K map
1)F(A,B,C,D,E)=∑(0,2,4,6,9,13,21,23,25,29,31)
2)F(W,X,Y,Z)=∑(0,1,2,4,5,6,8,9,12,13,14)
3) F=A1C+A1B+AB1C+BC
4)F(A,B,C,D)= ∑ (0,1,2,3,6,10,11,14)
5) F(A,B,C,D)= ∑(0,1,2,3,6,10,11,14)
1)Design 4 bit combinational circuit 2’s complement, the output generates the 2’s complement of the input binary number,show that the circuit can be constructed using EX-OR gates?
2)Design a code converter that converts decimal digits from 8-4-2-1 code to binary?
3)Design a combinational circuit that converts a 4 bit grey code to 4 bit binary number, Implement using EX-NOR gates?
4) Implement with a mux
a) F(A,B,C,D)= Σm(0,1,3,4,8,9,15);
b)F1(A,B,C,D)=Σ (1,3,4,11,12,13,14,15);
c)F2(A,B,C,D)= Σ(1,2,5,7,8,10,11,13,15))
d) Construct 16x1 multiplier with two 8x1 ans 8 one 2x1 multiplier using block diagram
5)a)Draw the logic diagram of 2-4 line decoder using
a) NOR gates b) NAND gate
b) Construct 4 to 16 line decoder with four 3x8 decoder
1. How do you convert a XOR gate into a buffer and an inverter (Use only one XOR gate for each)?
2. Implement a 2-input NAND gate using a 2x1 mux.
3. How can you convert a SR flip-flop to a JK flip-flop?
4. What are the differences between a flip-flop and a latch?
5. What is the difference between Mealy and Moore FSM?
6. Give the transistor level circuit of a CMOS NAND gate.
7. Give two ways of converting a two input NAND gate to an inverter.
8. Give the design of 8x1 multiplexer using 2x1 multiplexers.
9. Design 2 input AND, OR and XOR gates using 2 input NAND gate.
10. Implement a D-latch using 2x1 multiplexers.
11. Implement a full adder using muxs.
12. Realize A+(B.C+D.E)’ using CMOS.
Q : If inverted op of D ff is connected to input of ff how the flop behave ??
A : It behave as T flipflop
Q : Design a circuit for dividing input frequency by 2 ?
A : please give input frequency as the clock of T flip flop & input of flop is 1. Output will be input
clock divide by 2 .
Q : What are the different type of adder implementation ?
A : Carry Ahead,And & Xor combinational circuit , Ripple carry .
Q: Give the Truth Table for a Half Adder ?? Give gate level Implementaion of it ??
A:
A B Y Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Y = A xor B , Carry = A and B
Q : Design OR gate from 2:1 mux
A : assume that A & B are the input of OR gate . Then
Give A as sel pin of 2:1 mux , B to the 0th pin Mux & 1 to 1th pin of Mux
Q : Design a D FF from two latches ?
A : Connect two latches serialy , First latch enable pin positive level & second latch enable pin
as negative level or vice versa . Connect clock to enable pin it will work as FF .
Guideline To Avoid Race
Condition
(A). Do not mix blocking and nonblocking statements in same block.
(B). Do not read and write using blocking statement on same variable.( avoids
read write race)
(C). Do not initialize at time zero.
(D). Do not assign a variable in more than one block.( avoids write-write race)
(E). Use assign statement for inout types of ports & do not mix blocking
and nonblocking styles of declaration in same block. It is disallow variables
assigned in a blocking assignment of a clocked always block being used outside
that block and disallow cyclical references that don't go through a
non-blocking assignment. It is require all non-blocking assignments to be in a
clocked always block.
(F). Use blocking statements for combinational design and nonblocking for
sequential design. If you want gated outputs from the flops, you put them in
continuous assignments or an always block with no clock.
Avoid
Race Between Testbench And DUT
Race condition may occurs between DUT and testbench. Sometimes verification
engineers are not allowed to see the DUT, Sometimes they don't even have DUT to
verify. Consider the following example. Suppose a testbench is required to wait
for a specific response from its DUT. Once it receives the response, at the
same simulation time it needs to send a set of stimuli back to the DUT.
Most Synchronous DUT works
on the posedge of clock. If the Testbench is also taking the same reference,
then we may unconditionally end in race condition. So it~Rs better to choose
some other event than exactly posedge of cock. Signals are stable after the
some delay of posedge of clock. Sampling race condition would be proper if it
is done after some delay of posedge of clock. Driving race condition can be
avoided if the signal is driven before the posedge of clock, so at posedge of
clock ,the DUT samples the stable signal. So engineers prefer to sample and
drive on negedge of clock, this is simple and easy to debug in waveform
debugger also.
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