STA
1.From
rtl through Verdi how can we get the
constraint info.
If we want
to work with 5 Mhz lets go with 6mhz
By soucing
Verdi we can get it from the waveform the constraint info.
Specs we know clock and reset only.
2. Will we
do the STA flow as below.
set
search_path
set
link_path
read_db
read_verilog
link_design
3. Then we
do the constraints like create_clock and if needed create_generated clock
Provided
inputs from the designer
4. set_clock_transition
set_clock_uncertainty( basis-oscillator
spec,pll,vco)
set_clock_latency
5.In the
next step
we do
set_input_delay
set_output_delay
set_min_pulse_width(clock)
if the
guide tells->(all analog part)
set_max_capacitance
set_min_capacitance
set_max_transition
6.Then timing
paths and exceptions
set_multicycle_paths
All approaches for MCP and false
path
set_false_path
neg slack
if we set false path –goes to positive
slack
set_min_delay
set_max_delay
set_disable_timing( timing arc)
PHY TEAM
set_operating_condition
set_driving_cell
set_load
set_wire_load_model
7.case
set_case_analysis
Logical
exclusive (0 and 1)
On what
scenario we do?
mutally exclusive ?( dependency between 2 conditions)?
If we
check the fast mode slow mode not occur.
set_mode? didnot get this(tsmc buffer name lib)
8.Back
annotation(pd)
set_sdf
read_parasitics(.def)
from synthesis
8. analog
read_ocvm
set_
set_aocvm_coefficient
set_aocvm_table_group
set_ocvm_table_group
set_timing_derate
9.specify
power info
10.signal
integrity
set_app_var
si_enable_analysis.true
read_parasitics
_keep_capacitance_coupling
On what
scenario we do?
Is this
for analog ?
11.violation
checks
set_latch_loop_breaker
get_latch_loop_breaker
set_multi_input_switching_coefficient
12. check
design and analysis setup
check_timing
check_constraints
report_design
report_port
report_net
report_clock
report_wire_load(not)
report_path_group
report_cell
report_hierachy
report_reference
report_lib
13.report
and debug analysis,results,GUI
report_global_timing(primetime)
report_timing
report_constraint
report_bottleneck
report_analysis
report_delay_calculation
update_timing
will we
run this?
14.ECO
flow
set_eco_options
fix_eco_drc
fix_eco_timing
fix_eco_power
write_changes
15.saving
PT session
save_session
In the eco
timing option there is options to add buffer,upsize /downsize inverter.
On what
basis we will do all fix?
Setup violation:
1.Reduce
the amount of buffers in the path.
2.Replace
buffers with 2 inverters placed further apart.Manually
3.HVT swap
with LVT swap and vice versa(PD team)
4.Increase
driver size or decrease driver size (PD team)
5.insert
buffers
6.insert
repeaters
7.adjust
cell position in layout ( move the
cell)?( PD team)
8. clock
skew( PD team)
Adding
delays between path
Pipeline-logic
Hold violations
a.add
delay-add buffer/inverter /delay cells to datapath
b.increase
size of certain cells in data path
how do we
find?
How many
cells in the path?
How many
combo logic cells?
Pipeline-
we write logic
Cut insert
FF
Upsize
inverter
Setup
scenario:
Negative
slack=>setup violation
WNS=-ve
Hold
scenario:
Worst case
report:Slow slow corner
Each gate
/component takes 3 values-slow,fast,typical
Slow is
considered in time
Fast in
the hold violation
Area
constraints :0
Inputs of STA
netlist
constraints
net delays
parasitics
(spef)
sdf
models(lib/db)
1. false
path
Regarding
the false path: We check unrelated clock
Any other
methods
Regarding
multicycle path:
Schematics
Slacks
will inform
Critical
path =>REPORT paths (four paths)
Single
cycle path=>input to reg path
Launch
path =>reg to reg
Capture
path=>reg to reg
Between
reg to reg –there is combo
Longest path –input to combo
Longest
path(worst path,; late path,max path,max delay path)
Shortest
path(best path,early path,min path,min delay path)
