IC Design : ASIC RTL

Asic rtl interviews

1.Introduction

2.50MHz ->100MHz.where you pass the data signal.

3.different synchronization.

4.why gray code?

5.Asynchronous FIFO.

6.Clock path

7.False path

8.Timing constraints

9.Multicycle path

10.Two flipflop with a combo logic.find setup time.

12.how to add skew.

13.i2c,spi,UART

14.I2C working more

15.Arbitration,bit banging ,clock stretch

16.2 master -2 slaves .how will you give priority?

17.open drain

18.pull up resistor.

19. asynchronous FIFO.Why gray coding?

20. asynchronous FIFO.synchronous mechanism

21.binary encoding vs one hot encoding

22.why gray coding is not used .how it differs in binary coding.

23.mealy vs moore

24.what design we use mealy?

25. what design we use moore?

I2c timing diagram with AHB

SPI clock

Clock polarity of spi

I2c clock used

I2c,spi speed

Frequency of peripherals

AHB-APB interconnect –APB

Timing issues and synchronization

UPF-How to do?

How many power domains in projects

Supply port,supply net

Isolation strategies –all

How to do isolation,level shifting,retention strategy?

USB pins to AHB

Is it usb PHY

Synchronization mechanism
AXI Transaction –how interleaving
Write interleaving in AXI

Divergence,Convergence,Reconvergence

STA-DC Compiler

PCIE3,DDR3

ASIC RTL porting.Clock gating how.
How many clocks worked asynchronous.

how to resolve setup and hold violations
I2c spi interface
Latches vs Flipflop
Why default in latch

Calculate FIFO depth.75MHz 128 Mbits and 100MHz 64Mbits
CDC-Synchronization schemes
Toggle synchronizer set up,working
Pulse synchronizer setup working
Why reset is significant?
what is reset recovery,reset removal?
What is asynchronous reset?

.If without reset will it works.
Timing constraints if we use asynchronous FIFO
Input delay ,output delay
Mindelay,max delay
FIFO depth achieved is 520.FIFO requirement is 520.How to achieve in FPGA?
Setup,hold time
Reset synchronizer
Reset synchronizer used in fpga ?
Asynchronous reset used?advantages and disadvantages.syn reset used ,advantages disadvantages

Best case,worst case
Timing constraints in existing project?
.If we have 200MHz and 50MHz ASYNCHRONOUS CLOCK DOMAIN.How to synchronise.

.Timing constraints for the same.
I2C,SPI

Guidelines for clocks and resets

A simple clocking structure is easier to understand, analyze, and maintain.
In addition to this, a simple clocking structure helps to produce better synthesis results.

Avoid mixed clock edges
Avoid clock buffers
Avoid gated clocks
Avoid internally generated clocks
Gated clocks and low power designs
Avoid internally generated resets

Ideal clocking structure

The preferred clocking structure is

A single global clock, and
Positive edge-triggered flops as the only sequential devices.

Avoid Mixed Signal

Guideline

􀃂 Avoid using both positive-edge and negative-edge triggered flip-flops.

Mixed clock edges can be used for very aggressive timing goals, such as DDR (double data rate).The cares must be taken.

􀃂 The duty cycle is critical, since it is a critical issue in timing analysis in addition to frequency.􀃂

Scan-based testing requires separate handing of positive and negative triggered flops.

Avoid clock buffers

Guideline

Avoid hand instantiating clock buffers in RTL code.
Clock buffers are morally inserted after synthesis as port of the physical design.
In synthesizable RTL code, clock nets are normally considered ideal nets, with no delays.
During place and route, the clock tree insertion tool inserts the appropriate structure for creating as close to an ideal, balanced clock distribution network as possible.

Avoid Gated clock

Guideline

􀃂 Avoid coding gated clocks in RTL,since clock gating circuits tend to be technology specific and timing dependent.

Improper timing of a gate clock can cause 􀃂a false clock or glitch,􀃂 Set-up and hold time violation.

Gated clock and low power design

Guideline

􀃂 Keep the clock and/or reset generation circuitry (for a gate clock,an internally generated clock or reset) as a separate module at the top level.

􀃂 Partition the design so that all the logic in a single module uses a single clock and a single reset.

Isolating clock and reset generation logic in a separate module enables to use the standard timing analysis and scan insertion techniques.

Avoid internally generated reset

Guideline

Avoid internally generated,conditional reset if possible. Generally, all the registers in the macro should be reset at the same time.

If a conditional reset is required, create a separate signal for the reset signal, and isolate the conditional reset logic in a separate module.

Coding for synthesis

In order to create code that
achieves the best compile times and
synthesis results.
Testability
Performance
Simplification of static timing analysis
Gate-level circuit behavior that matches that of the original RTL
code

Infer registers

􀀟Avoid latches
􀀟 Avoid combinational feedback
􀀟 Specify complete sensitivity lists
􀀟 Blocking and non-blocking assignments
􀀟 Case statements v.s. if-then-else statements
􀀟 Coding state machines

Infer registers

Guideline
􀃂 Registers (flip-flops) are the preferred mechanism for sequential logic (as compared to latches).
􀃂 Use designer’s reset signal to initialize registered signals.
􀂋 Do not use initial statement to initialize the signal, since it is not synthesizable construct.
􀃖 These can cause mismatches between pre-synthesis and portsynthesis simulation

// process with synchronous reset

always @ (posedge clk)
begin
if (reset == 1’b1) begin
… something …
end else begin
… something else …
end
end // INFER_REG_PROC

// process with asynchronous reset

always @ (posedge clk or negedge rst_n)
begin
if (reset == 1’b0) begin
… reset behavior
end else begin
… normal behavior
end
end // INFER_REG_PROC

Avoid latches

Rule: avoid using any latches

Latch

􀃂 When CLK = 1, latch is transparent
􀂋 D flows through to Q like a buffer
􀃂 When CLK = 0, the latch is opaque
􀂋 Q holds its old value independent of D
􀃂 a.k.a. transparent latch or level-sensitive latch

What makes unintended latch inference.

􀃂 Missing assignment
􀃂 Missing condition
􀀟 How to avoid the unintended latch inference.
􀃂 Avoid latch by fully assigning
outputs for all input conditions using else and default.

// process causes latch inference

always @ (a or en) if (en==1’b1) q = a;
// its semantics imply that q must hold
// its old value when en is low.

// process without latch inference
always @ (a or en) if (en==1’b1) q = a; else q = 1’b0;

Avoid combinational logic

Guideline
􀃂 Avoid combinational feedback

Specify complete sensitive list

include a complete sensitivity list in each of always blocks.

􀃂 If not, the behavior of the presynthesis design may differ from that of the post-synthesis netlist.

Guideline

􀃂 For combinational blocks (blocks with no registers or latches), the sensitivity list must include every
signal that is read by the process.
􀃂 For sequential blocks, the sensitivity list must include the clock signal that is read by the
process.
􀃂 Make sure the sensitivity lists contains only necessary signals.
􀂋 Adding unnecessary signals to the sensitivity list slows down simulation.

Blocking assignments execute in sequential order,
􀀟 While non-blocking assignments execute concurrently.

Rule: use non-blocking
assignment (<=) in always
blocks.

Race

always @ (posedge clk) begin
a = y;
end
always @ (posedge clk) begin
c = a

To avoid race condition, Use non-blocking assignment

always @ (posedge clk) begin
a <= y;
end
always @ (posedge clk) begin
c = a
end

case statement

A case statement infers a singlelevel multiplexer,
􀀟 While an if-then-else statement infers a priority-encoded, cascaded combination of multiplexers.

Guideline

The multiplexer is a faster circuit.

Coding state machine

Guideline
􀃂 Separate the state machine HDL description into two processes, one for the combinational logic and one for the sequential logic.

􀃂 Use `define statements to define the state vector.

􀃂 Keep FSM logic and non-FSM logic in separate modules.

􀃂 Assign a default state for the state machine.

reg [1:0] state, next_state; // FSM state
//----------------------------------------------
parameter IDLE = 2'h0;
parameter FOUND = 2'h1;
parameter MODULUS = 2'h2;
parameter DONE = 2'h3;
//----------------------------------------------
always @ (state or input)
case (state)
IDLE: begin
…
next_state <= FOUND;
end end // IDLE
FOUND: begin
…
next_state <= DONE;
end // FOUND
endcase
always @ (posedge clk or negedge rst_b)
if (rst_b == 1’b0) state <= IDLE;
else state <= next_state;

Partioning design for synthesis

Register all outputs
􀀟 Locate related combinational logic in a single module
􀀟 Separate module that have different design goals
􀀟 Asynchronous logic
􀀟 Arithmetic operations: merging resources

Register all outputs

Guideline
􀃂 For each block of a hierarchical design, use register for all output signals.
􀂋 Registering the output signals from each block simplifies the synthesis process because it
makes output drive strengths and input delays predicable.

Keep related combinational logic together in the same module.

Guideline

􀃂 Keep related combinational logic together in the same module.

􀂋 Synthesizer has more flexibility in optimizing a design when related combinational logic is located in
the same module.
􀂋 Keep related combinational logic in the same module also eases time budgeting and allows for
faster simulation.

Separate modules that have different design goals

Guideline

􀃂 Keep critical path logic in a separate module from non-critical path logic.
􀂋 Synthesizer can optimize the critical path logic for speed, while optimizing the non-critical path
logic for area.

Avoid asynchronous logic

Guideline
􀃂 Avoid asynchronous logic.
􀃂 If asynchronous logic is required,
partition the asynchronous logic in a
separate module from the
synchronous logic.
􀃂 Isolating the asynchronous logic in a
separate module makes code
inspection much easier.
􀃂 Asynchronous logic need to be
reviewed carefully to verify its
functionality and timing.

Avoid mcp

Guideline

􀃂 Avoid multi-cycle paths
􀂋 In multi-cycle path, data traverse the path from one register to another for multiple clock cycles.
􀂋 Multi-cycle path is more difficult to analyze correctly.
􀃂 If needed, keep point-to-point exceptions within a single module.

Avoid glue logic at top level

Guideline
􀃂 Do not instantiate gate-level logic at the top level of the design hierarchy.
􀂋 Let design hierarchy contain gates
only at leaf levels of the hierarchy
tree.

BEST CODING PRACTICES

Addressing basic coding practices, focusing on lexical conventions and basic RTL constructs.

General naming conventions
􀀟 Including headers in source files
􀀟 Use comments
􀀟 Keep commands on separate lines
􀀟 Line length
􀀟 Indentation
􀀟 Do not use HDL reserved words
􀀟 Port ordering
􀀟 Port maps and generic maps
􀀟 Use functions

Rule: develop a naming convention for the design, which must be documented and used consistently throughout the design.

Guidelines

􀃂 Use lowercase letters for all signal names, variable names, and port names.
􀃂 Use uppercase letters for names of constants and user-defined types.
􀃂 Use meaningful names for signals, ports, functions, and parameters.
􀃂 Use short name, but descriptive names for parameters.
􀃂 Use ‘clk’ as the prefix for all clock signals.
􀃂 Use ‘_n’ (or ‘_b’) as the postfix for all active all signals.
􀃂 Use ‘rst’ for reset signals. If it is active low, then use ‘rst_n’.
􀃂 Use a consistent ordering of bits for multi-bit buses.
􀃂 Use the same name or similar names for ports and signals that are connected.

Include header in source file

Rule: include a header file at the top of every source file, including scripts.
􀀟 Syntax of header
􀃂 Filename
􀃂 Author
􀃂 Description of functions
􀃂 List of key features
􀃂 Date the file was created
􀃂 Modification history including date, name of modifier, and description of the change

use comments
Rule: use comments appropriately to explain all processes, functions, and declarations of types and
subtypes.

Guidelines

􀃂 Use comments to explain ports,signals, and variables, or groups of signals or variables.
􀃂 Comments should be brief, concise,and explanatory.
􀃂 Comments should be placed logically, near the code that they describe.

Keep commands on separate line
Rune: use a separate line for each
HDL statement.
􀃂 In order to be more readable and maintainable.

Rule: keep the line length to 72 character or less.

Indentation

Rule: use indentation to improve the readability of continued code lines and nested loops

Guideline

􀃂 Use indentation of 2 spaces.
􀂋 Large indentation restricts line
length when there are several
levels of nesting.
􀃂 Avoid using tabs.
􀂋 Differences in editors and user setups make the positioning of tabs unpredictable and can corrupt the intended indentation.

Never use hdl reserved words

Rule: do not use HDL (Verilog and VHDL) reserved words for names of
any elements in RTL source files.
􀃂 Macro designs must be translatable from Verilog to VHDL and vice verse.

Port ordering

Rule: declare ports in a logical order,and keep this order consistentthroughout the design.
Guideline
􀃂 Declare one port per line, with a comment following it.
􀃂 Declare the ports in the following order.
􀂋 inputs
􀃖 Clocks, resets, enables, controls,data and address
􀂋 Outputs
􀃖 Clocks, resets, enables, controls, Data

Port maps and generic maps
Guideline: always use explicit
mapping for ports and generics,
using named association rather than
positional association
Guideline
􀃂 Leave a blank line between the
input and output ports to improve
readability.

//------------------------------------------------------
gcd Ugcd (
.clk (clk),
.reset(reset),
.A (A),
.B (B),
.valid (valid),
.C (C),
.done (done)
);

Use functions

Guideline
􀃂 Use functions when possible,
instead of repeating the same
sections of code

//------------------------------------------------------
function [`WIDTH-1:0] conv_addr;
input [`WIDTH-1:0] input_addr;
input offset;
begin
……
end
endfunction

Coding for portability

Create code that is technologyindependent,compatible withvarious simulation tools, and easily
translatable from Verilog to VHDL(or from VHDL to Verilog).

Do not use hard-coded numeric values

􀀟 Include files
􀀟 Avoid embedding dc_shell scripts
􀀟 Use technology-independent Libraries
Do not use hard-coded numeric values
Guideline

􀃂 Do not use hard-coded numeric values.
􀂋 Use constants instead of hardcoded Values

Include files
Guideline
􀃂 Keep the `define statements for a
design in a single separate file and
name the file
DesignName_params.v.
Avoid debugging dc_scripts
Guideline
􀃂 Avoid using dc_shell script in the source code in order to portability reason.

Use technology independent lib

Guideline

􀃂 Use the DesignWare Foundatioin Library to maintain technology independence.
􀃂 Avoid instantiating gates in the design
􀂋 Gate-level design is hard to read,and thus difficult to maintain and reuse.
􀂋 Technology-specific gates make the design non-portable.
􀃂 Use GTECH library, if gate must be used.

􀂋 GTECH library (Synopsys generic technology library – one of technology-independent library)
contains technology independent logical components

􀃖 AND, OR, NOR, flip-flops, ..

Linting

Lint uses

Types of lint issues

Lint rules

setup environment

Lint tool version

waiver setup

Is the rule set by customer or the designer?

Lint rules with examples

Lint targets

array rules

multiple driver rules
RTL coding rules

verilog constructs

fork and join is synthesizable or not

synchronous reset vs asynchronous reset

function vs task

is task synthesizable

full case vs parallel case

specify block

procedural assignment

continuous assignment

mux logic different styles in verilog

full adder different styles in verilog

intial abd always differences

verilog vs vhdl differences

Lint flow in spyglass

Lint flow in Superlint

Rules in spyglass

generate statement in verilog

Clock domain crossing

In digital electronic design a clock domain crossing (CDC), or simply clock crossing, is the traversal of a signal in a synchronous digital circuit from one clock domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary.

A CDC signal is a signal latched by a flip-flop (FF) in one clock domain and sampled in another asynchronous clock domain. Transferring signals between asynchronous clock domains may lead to setup or hold timing violations of flip-flops. These violations may cause signals to be meta-stable.

Even if synchronizers could eliminate the meta-stability, incorrect use, such as convergence of synchronized signals or improper synchronization protocols, may also result in functional CDC errors.

Digital system consists of combinational and sequential logic. Clock triggers flops leading to state changes (viz. State Machines). Clock is the fastest signal in a synchronous system.

A clock has Period of repetition (linked with its frequency) .Phase depicts rise & fall transitions

A flop can be triggered thru any of clock phases.

A synchronous system is composed of a single electronic oscillator that generates a clock signal, and its clock domain—the memory elements directly clocked by that signal from that oscillator, and the combinational logic attached to the outputs of those memory elements.

Because of speed-of-light delays, timing skew, etc., the size of a clock domain in such a synchronous system is inversely proportional to the frequency of the clock.

In early computers, typically all the digital logic ran in a single clock domain. Because it is difficult to carry digital signals above 66 MHz on standard PCB traces (and the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that speed invariably are single-chip CPUs with a PLL or other on-chip oscillator, so all the really high-frequency signals stay inside the chip and are never carried by the PCB traces.

At first each CPU chip ran in its own single clock domain, and the rest of the digital logic of the computer ran in another slower clock domain. A few modern CPUs have such a high speed clock that designers are forced to create several different clock domains on a single CPU chip.

SYNCHRONOUS IN DIGITIAL

• All flip-flops clocked by one common clock

• Reset only used for initialization

• Races and hazards are no problem

Three things must be ensured by the designer:

• Minimize and determine clock skew

• Account for flip-flop setup and hold times

• Reliably synchronize asynchronous inputs

Why synchronous design?

• Hazard

Problems due to timing that cannot be observed from functional analysis

• Static hazard: possibility of a brief signal value change when the signal was expected to be stable, due to timing (glitch)

A static hazard can occur when changing a single input variable causes a jump from one prime implicant to another

Solution: include an additional prime implicant

• Dynamic hazard: possibility of multiple output transitions caused by a single input transition due to multiple signal paths with different delays

• In order to avoid hazards and races, synchronous design is used

• In synchronous design a single common clock is used and reset is only used for initialization

• The only considerations in synchronous design are the flip-flop setup and hold times, clock skew and asynchronous input synchronization

• Asynchronous inputs are commonly synchronized using 2 flip-flops clocked with the synchronous system clock

• Synchronization should only be done in one place

• In bus transfers, synchronize only the control signals or use a FIFO

Design trade offs

• Performance

– Latency

– Throughput

– Delay (timing)

• Area

– Gates (ASIC)

– Flip-flops/LUTs (FPGA)

• Power consumption

– Dynamic

– Static

– Leakage

• Design for High Throughput

– Definition: High data rate, acceptable latency

– Technique: Pipelining

• Design for Low Latency

– Definition: Output available as soon as possible

– Technique: Parallelism, Removal of pipelining

• Design for Timing

– Definition: High clock speed, low delay between registers

– Technique: Add intermediate registers

Design for area:

• Resource (logic) sharing

• Rolling up the pipeline

Design for low power:

• Power components:

• Dynamic power consumption (switching): power consumed due to charging and discharging parasitic capacitances on gates and wires

• Static power consumption: Power consumed when no switching

• Leakage current power consumption:

Design for power:

• Clock Gating

• Dual-edge triggered Flip-Flops

• Lowering core voltage

Clock domain crossing

Because of speed-of-light delays, timing skew, etc., the size of a clock domain in such a synchronous system is inversely proportional to the frequency of the clock. In early computers, typically all the digital logic ran in a single clock domain. Because it is difficult to carry digital signals above 66 MHz on standard PCB traces (and the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that speed invariably are single-chip CPUs with a PLL or other on-chip oscillator, so all the really high-frequency signals stay inside the chip and are never carried by the PCB traces.

Different clock domains have clocks which have a different frequency, a different phase (due to either differing clock latency or a different clock source), or both. Either way the relationship between the clock edges in the two domains cannot be relied upon.

Synchronizing a single bit signal to a clock domain with a higher frequency can be accomplished by registering the signal through a flip-flop that is clocked by the source domain, thus holding the signal long enough to be detected by the higher frequency clocked destination domain.

To avoid issues with meta-stability in the destination domain, a minimum of 2 stages of re-synchronization flip-flops are included in the destination domain.

Synchronizing a single bit signal traversing into clock domain with a slower frequency is more cumbersome. This typically requires a register in each clock domain with a form of feedback from the destination domain to the source domain, indicating that the signal was detected.[2]

In some cases, clock gating can result in two clock domains where the "slower" domain changes from one second to the next

A signal to another clock domain

Let's say a signal from clkA domain is needed in clkB domain. It needs to be "synchronized" to clkB domain, so we want to build a "synchronizer" design, which takes a signal from clkA domain, and creates a new signal into clkB domain.

In this first design, we assume that the "Signal-in" changes slowly compared to both clkA and clkB clock speeds.

All you need to do is to use two flip-flops to move the signal from clkA to clkB

Data bus to another clock domain

To move a data bus (2 bits wide or more) from one clock domain to another, we have several techniques to our disposal.

Gray code: If the data bus is a monotonic counter (i.e. only incrementing or decrementing), we can convert it to a gray code, which has the ability to cross clock domains (under certain timing conditions).

Data freeze: If the data bus is non-monotonic, use a flag to signal the other domain to capture the value (while it is frozen in the source clock domain).

Data burst: If the data bus has many consecutive values that need to cross the clock domain, use an asynchronous FIFO, where you push values from the source clock domain, and read back values from the other domain.

Custom synchronization techniques for CDC paths

Half synchronizer

When the destination flip-flop and the synchronizing flip-flop(s)) are triggered at different edges of the same clock.

Half-Cycle synchronizers are used if only the half cycle is enough to stop the metastability.

Synchronizer works faster as you would pass your data in next inactive clock edge itself.

Generally used for slow clock frequencies.

Pulse synchronizer

Two asynchronous clocks Clk1 and Clk2.

Transfer a pulse “Trig” launched at clock Clk1 to Clk2 domain. use a flop whose D input is tied to “1” to capture this pulse. synchronize the output of this flop to destination domain using 2- DFF scheme.

use an additional flop after synchronizer stage to generate the pulse (here at out) in Clk2 domain which is again high only for one clock cycle in the shown case.

The designer may extend the pulse in destination domain if required. The same generated pulse is used to reset the initial capturing flop.To transfer a single pulse from source domain we require three clock cycles of destination domain.

Deployed in cases only where destination frequency is at least three times faster than source frequency.

Clock gating based synchronizer

Get rid of CDC issues if we ensure that the clock of destination flip-flop is turned off while the data is toggling. The enable is generated from the source domain and is synchronized to destination domain using 2-DFF scheme.Whenever we want to toggle the data we first gate the destination clock through enable of cg cell.

The data is transferred and the destination clock is enabled afterwards. For a single bit transfer it may be an overhead. Extended for transfer of complete data bus.

There has been a general practice of using special library cell for 2-DFF synchronizer. It has following advantages.

• a. Special dedicated Flip-Flop for synchronizers are designed with very special constraints on minimizing the window of sensitive time when sampling the input signal.

• b. This also ensures that while placement the two Flip-Flops are placed close to each other.

Asynchronous FIFO

CDC Bug Anatomy

Missing or incorrect synchronizer

Incorrectly implemented CDC Protocol

Design doesn't account for non-deterministic delay through synchronizers

MULTIPLE CLOCK DOMAINS.WHY?

To reduce Clocktree balancing complexities.

Consider clocks to various blocks as asynchronous.

CDC PROBLEMS

Four main problems associated with CDCs:

Metastability

Data hold in fast-to-slow crossings

Data correlation and race conditions

Issues related to complex synchronizers

When clocks are a-synchronous, the signals that interface between are called clock domain (CDC) paths. Within each domain, data transfer is protected by Setup & Hold checks of flops. No check exists on CDC path

CLOCK GROUPS

• All that are part of the same clock domain form a clock group.It identify various clock domains.

MTBF

• Reciprocal of failure rate.

• Should be as high as possible

• Failure means signal goes metastable after first stage synchronizer and continues to be metastable one cycle later when it is sampled in the second stage synchronizer flop.

CDC SOLUTIONS

Single bit crossing

Data/ control bit.

Multi bit crossing

Data bit crossing

Multibit crossing

SOLUTIONS:SINGLE BIT

Ensures that destination should not enter metastable state.

MULTIBIT

Multibit data can be

• Binary counter data

• Burst data

• Stable data with valid signals

2 flop syn doesnot work in burst data and counter output.

Use 2 flop sync to sync the valid(1 bit signal) and sample data at receiver domain.

Why no 2flop syn used?

Multiple bit changes at the same time.011-100

Different sync may produce random value

Solution:

Convert binary -gray

use 2 flop syn at reciver domain to sample the gray output from tranmit domain.

In gray one one output changes at a time.

Example:011-010

Stable data with valid signal

• In order to synchronize data,a control pulse is generated in source clock domain when data is available at source flop.

• Control pulse is then syn using 2 FF Syn or pulse sync depending on clock ratio between source and destination domain.

• Sync control pulse is used to sample the data on the bus in destination domain.

• Data should be stable until it is sampled in destination domain.

BURST DATA

• Burst means changing data at every clock.

• 2 Flop syn doesnot work.

• Use asynchronous FIFO.

Multibit control signals

• Cannot use different synchronization at destination domain.

• Skew can result in sampling of different control bits at different clock edges which can result in delays in control bits.

Solution:

Consolidation of control bits.

FIFO techniques.

Consolidate load and enable and register in the source and use synchronise output in destination domain.

COMBO LOGIC BEFORE SYNCHRONIZER

• Static cdc checks for combo logic in every cdc path that has detected synchronizer.

Combinational logic in a synchronization path is a significant problem because data is used to determine an acceptable failure rate on synchronization paths assume a signal transition on a CDC signal during each clock period.

CDC PROBLEM

• Input to combo logic changes to source clock.

• Combination logic creates glitches.

• Glitches settle before next clock edge.

• Destination captures stable data.

CDC PATH

To avoid issues with meta-stability in the destination domain, a minimum of 2 stages of re-synchronization flip-flops are included in the destination domain.

In some cases, clock gating can result in two clock domains where the "slower" domain changes from one second to the next

A signal to another clock domain

In this first design, we assume that the "Signal-in" changes slowly compared to both clkA and clkB clock speeds.

All you need to do is to use two flip-flops to move the signal from clkA to clkB (to learn why, get back to the links).The two flip-flops have the side-effect of delaying the signal.

For example, here are waveforms where you can see the slow moving signal being synchronized (and delayed) to clkB domain by the two flip-flops:

A flag to another clock domain

If the signal that needs to cross the clock domains is just a pulse (i.e. it lasts just one clock cycle), we call it a "flag". The previous design usually doesn't work (the flag might be missed, or be seen for too long, depending on the ratio of the clocks used).

We still want to use a synchronizer, but one that works for flags.

Data freeze: If the data bus is non-monotonic, use a flag to signal the other domain to capture the value (while it is frozen in the source clock domain).

• Recovery time

Minimum time required between the release of an asynchronous signal from active edge to next active clock edge.

For instance: time between the reset and clock transitions of a flip flop

• Removal time

Minimum amount of time between an active clock edge and the release of an asynchronous control signal.

1) What are the major issues for Clock Domain Crossing ?

They are 3 major problems for clock domain crossing:

A. Metastability - the transaction of data violated the setup or hold time of the destination FF. It caused the ouput may oscillate for an indefinite amount time.
      The Metastability may lead to the high current or even burn out of the chip. It also caused functional issue and timing issue.

B. Data Loss - whenever a new source data is generated, it may not be captured by the destination domain in the very first cycle of the destination clock because of metastability. Plus the different clock frequency of source and destination may also caused the data loss.

C. Data Incoherency - whenever new data is generated in the source clock domain, it may take 1 or more destination clock cycles to capture it, depending on the arrival time of active clock edges.

2) 4 common method to solve the clock domains crossing problems

There are 4 common method to solve the clock domains crossing problems:

1. MUX recirculation technique

The MUX recirculation technique is shown as below:

A control signal EN, generated in the source domain is synchronized in the destination domain using a multi-flop synchronizer. The synchronized control signal EN_Sync drives the select pin of the muxes, thereby controlling the data transfer for all bits of the bus A.

In this way, individual bits of the bus are not synchronized separately, and hence there is no data incoherency. However, it is important to ensure that when the control signal is active, the source domain data A[0:1] should be held constant.

2. Handshake synchronization

A very common and robust method for synchronizing multiple data signals is a handshake technique as shown in Figure. This is popular because the handshake technique can easily manage changes in clock frequencies, while minimizing latency at the crossing.

3. FIFO synchronization

FIFO is used when you need to transfer data from one clock domain (clock domain at which you store data) to another clock domain, it grantees that the data will cross from that domain to the other (smoothly) if the Asynchronous FIFO is designed right (Async FIFO usually will include Synchronizers or similar approaches) FIFO will introduce latency to assure that the data crosses the domain approriately

4. Multi-Flop Synchronizer

The synchronizers allow sufficient time for the oscillations to settle down and ensure that a stable output is obtained in the destination domain. A commonly used synchronizer is a multi-flop synchronizer

What are different ways to synchronize between two clock domains?

A very common and robust method for synchronizing multiple data signals is a handshake technique as shown in diagram below This is popular because the handshake technique can easily manage changes in clock frequencies, while minimizing latency at the crossing. However, handshake logic is significantly more complex than standard synchronization structures.

What is MTBF?

For most applications, it is important to calculate the Mean Time Before Failure / MTBF for any signal crossing a CDC boundary. In the context of MTBF, the failure means the output of the synchronizer still goes metastable. Obviously, a larger MTBF is favored over a smaller one, and the synchronization scheme needs to guarantee sufficient larger MTBF.

MTBF is inversely proportional to input data changing rate as well as receiving clock frequency. The faster of input data rate and receiving clock, the lower of MTBF.

n2terviewees often mix the concept of input data changing rate with sending clock frequency, and incorrectly think sending clock frequency does impact MTBF. Faster sending clock does not necessarily imply faster input data changing rate.

It is required to flop the data in sending clock domain before synchronized in receiving clock domain. The output of combo logic often have glitches, i.e., it requires some time to settle. Without data flopping, the input data changing rate is effectively increased in receiving clock domain, decreasing the MTBF of CDC circuit.

Why can synchronizers handle CDC?

The simplest synchronization scheme is back-to-back flop synchronizer. Even though the output of the first stage is metastable, the CDC signal still have one more cycle to settle to a stable logic value. herefore, synchronizers essentially increase the MTBF.

Clock Domains Crossing Issues

Clock Domain Crossing

CDC considerations to transfer a pulse

Transfer a pulse from slow to fast clock domain, and from fast to slow clock domain, require separate handling.

Generally speaking, passing a signal from slow clock to fast clock is not a problem, since the loss of a pulse is less likely to happen. Based on Nyquist Theorem, if receiving clock frequency is at least 2x of sending clock frequency, then there will be no sampling loss.

Passing a signal from fast clock to slow clock requires more careful handling. When passing a CDC signal through a 2 flip-flop synchronizer, if the CDC signal is wider than 1.5x the cycle width of the receiving domain clock period, then there will be no sampling loss. Sometimes, designers need to “stretch” the signal in the sending clock domain, to meet this “1.5x cycle width” requirement. Alternatively, designers can choose to use “handshake” to guarantee the robust signal transfer.

CDC considerations to transfer multi-bit signals

Multiple signals that are synchronized to one clock will experience small data changing skews that can occasionally be sampled on different rising clock edges in receiving clock domain. Thus we cannot simply use double flop synchronizers to transfer multi-bit signals.

There are several schemes that designers can choose from the toolkit:

1. Passing multiple CDC bits using gray codes

2. Passing multiple CDC bits using async FIFO if gray encoding cannot be achieved

3. Passing multiple CDC bits using handshake protocol

Que 2: Why Gray code counter is used in Asynchronous FIFO?

Ans: As we know that in Gray counter only 1 bit change happens from previous gray counter value. So, for example when we synchronize read pointer with write pointer clock, then there is possibility of metastability. So as there is only one bit change in the gray counter so even if there is metastability in gray counter when clock crossing, the gray counter value will be previous value. For example read pointer(gray counter) value is changing from 0110 to 0111 and synchronized with write clock then due to metastability(if occurs) read pointer still will be 0110, So suppose earlier FIFO Full Flag was high at read gray counter value 0110, Fifo Full will remain high 1 more clock cycle. That will not be an issue. If gray counter was not used for clock domain crossing then there was possibility of multi bit change of the counter and unpredicted(might be errornious) Flag(Fifo full or fifo empty) generation.

3: What care we take for Asynchronous reset in our design?

Ans: For Asynchronous reset we assert reset asynchronously and de-asserts reset synchronously. In our design to take care of this we have circuit which has 2 back to back Flip-Flop like synchronizer of which 1st Flop's D input is connected to '1' when asynchronous reset is active Low and use the output of second Flop as the reset for rest of the design.

4: Is Setup time, hold time required in Latch?

Ans: Yes, for a +ve level sensitive latch these are measured from falling edge and for -ve level sensitivity latch you should measure it from rising edge.
Setup time for a +ve level sensitive latch is that data should be stable for some time before the negedge of the latch enable signal so that data can be properly captured.

5: What are the deciding factors that we need FIFO?

1. When Bus widths are different : When data to be transferred from high bus width to lower bus width.
2.When we don't know what is relation between 2 clocks when data transferring from 1 clock to another clock.

6: Suppose we have a circuit like Flip-Flop but it has 4 states like normal flip flop has 2 states(0 or 1). Then how many these circuits(which has 4 states) are required for mod 10 circuit?

4^n >= 10 , so 2 these types of circuits required.

7: What is the difference between Blocking and nonblocking statements in verilog?

Blocking statements are sequential and executed one after another and represented by '='

example : always@(posedge clk)

begin
reg1 = d;
reg2 = reg1;
out = reg2;
end

If we see the above example code we will get 1 flip flop after synthesis.

Non Blocking statements are executed concurrently and
represented by '=>'

example : always@(posedge clk)

begin
reg1 <= d;
reg2 <= reg1;
out <= reg2;
end

If we see the above example code we will get 3 flip flop after synthesis.

8: why gate level simulation required?

GLS is a step in the Design flow to ensure that the design meets the functionality after placement and routing. To do GLS we Need post-routed netlist, sdf (standard delay format file).SDF contains all the delay information for the cell and the wire. The reasons for GLS are as:

1. To check if reset release, initialization sequence and boot-up is proper.

2. Since Scan insertions occur during and after synthesis, they are not checked by simulations.

3. STA does not analyze asynchronous interfaces.

4. Unwarranted usage of wild cards in static timing constraints set false and multi cycle paths where they don't belong. This can also be due to design changes, mis-understanding or typos.

5. X's in RTL sim can be pessimistic or optimistic. Any unintended dependencies on initial conditions can be found through GLS.

6. Design changes, wrong understanding of the design can lead to incorrect false paths or multicycle paths in the constraints.

7. Can be used to study the activity factor for power estimation.

8. It's an excellent feel good quotient that the design has been implemented correctly.

9: What is false path and Multi cycle path?

Ans: Multi cycle paths are those which require more than one clock cycles to complete due to high delays of big combo logic. while false paths are the path which will never be sentisized i.e. won't come in actual situation, that path will never occur.

10: What will happen if while synthesis we declare wrongly a path multi cycle path which was not multi cycle path.

Ans: When synthesis there is possibility that synthesizer may add some extra logic so the netlist we got now will not be able to complete this path in 1 clock, while in RTL simulation we will get output in 1 clock only, so there is possibility that there is mismatch in pre and post synthesis result.

In today’s complex system on chip (SoC) designs, different blocks are operating at different frequencies.if suppose a signal is travelling from one clock domain to another some problems are occur which are setup and hold violation, metastability and unreliable data transfers(data loss, data in coherency), CDC may occur when a signal is travelling from one block to another block which are operating at same frequency and their phases are not same.

To avoid this CDC issues there are some methods to solve:

· Handshake Signaling method.

· Asynchronous FIFO.

10. What is CDC? On which tool we run CDC? Why is it required?

11. How to know about the error details in Lintra as well as in questacdc/spyglass cdc?

12. How to debug errors/warnings in CDC?

13. If we got error "synchronizer is missing" from our tool. From this how we debug.

1. What is metastability and why is it a problem?

2. What is two flop synchronizer?

3. How MUX synchronizer helps to get rid of metastability?

4. What is MTBF and what is the relation of frequencies of two domains and MTBF?

5. What CDC technique is used for single bit data transfer from one domain to another clock domain?

6. How do you take care of CDC when signal is going from slow clock domain to fast clock domain?

7. How do you take care of signal bit crossing from fast clock domain to slow clock domain?

8. What CDC technique is used for data going from one clock domain to another clock domain?

9. What happens when combo output from one clock domain enters another clock domain?

10. Design a gray code counter and what is the advantage of gray code counters?

11. What is convergence and how do you fix?

12. What is divergence and how do you fix?

13. What is re-convergence and how do you fix?

14. How do you define clock and resets in SGDC file?

15. What is quasi_static in SGDC?

16. What is reset synchronizer?

17. What happens when reset is not synchronized and used?

18. What happens when same reset is synchronized twice and used in a clock domain?

19. What CDC technique do you use to transfer counter data from one domain to another domain?

20. What is closed loop and open loop CDC solution in transferring a bit form domain to another domain?

21. What are different CDC techniques used in designing ASYNC FIFOs?

22. What are different ways to synchronise between two clock domains?

23. What are logically connected clocks?

24. What are physically connected clocks?

25. What are asynchronous clocks?

26. How to reduce glitches while crossing from one clock domain to another?

27. What is single bit crossing?

28. What is multi bit crossing?

29. What is clock gating?

30. Explain spyglasss CDC flow?Explain jasper cdc flow?

31. What is a clock domain?

32. What is the effect of using combo logic before synchronizer?

33. What is asynchronous FIFO? When it is used in CDC bugs?

34. What is a clock group?

35. How to calculate FIFO depth?

36. What is fifo pointers?

37. How clock skew effects causes metastability?

38. What is slack?

39. What is clock clock uncertainity?

40. Can we use different clock synchronizers in the same design?

41. How does handshake based clock synchronizer work?

42. What is a reset synchronizer?

43. What are the different CDC schemes?

44. What is mean by coherency?

45.What are the structural issues in CDC?How do you overcome?

46.What are the functional issues in CDC?How do you overcome?

47.When do you perform case analysis?

48.What are the different types of reconvergence?

49.Timing waveform of convergence,divergence,reconvergence?

50.CDC .Why it is important.

51.Multibit synchronization.

52.For a bus,which synchronization is used.?

53.Pulse synchronizer setup and working.

54.Qualifier signals.

55.why 3 Flip flop synchronization is used.?

56.Waveform of the convergence,divergence,reconvergence.

57.When asynchronous FIFO is used?

58.When do you use handshake synchronizer?

59.Types of reconvergence.

60.sgdc constraint of clock and reset.

61.Gray code counter.advantages

62.rtl code for 2 flip flop synchronizer.

63.CDC schemes used.

64.For the counter design which synchronizer is used?

65.For a design first it toggles and then enters into burst mode.which synchroniser used?

66.What are logically connected and physically connected clock?

67.single bit and multi bit crossing.

68.Half synchronizer .rtl code for the same

69.clock gating synchronizer.where its is used.

70.CDC RULES

71.Clock group

71.FIFO wrapper.depth of fifo.if the reading clock is same as writing clock what happens?.FIFO signals

72 .Asynchronous FIFO.Conditions for overflow,threshold,underflow.verilog coding for all.

73.CDC violations and resolve

74.CDC constraints for design analysis and placement.

75.CDC design intent and benefits

76.CDC goals

77.Environment setup for cdc in the tool used

78.Version of the tool used.

79.If we insert level shifter the timing violation arise ,how do you resolve in low power?

80.RTL of toggle,mux,pulse,handshake synchronizer.

81.Why reset is important in soc?

82.Whatt is the need of reset synchronizer?.How does it works?

83.Synchronizer requirements.

84.XOR Synchronizer.

CAPTURING DESIGN INTENT CDC

• Different types of synchronizers.

Ø FIFO synchronizers for high volume data transfer.

Ø Handshake synchronizers for IP,portability and reuse.

Ø Data synchronizers -when a control signal from source domain synchronized using multiflop in destination domain performing as a qualifier responsible for ensuring that the data is stable when captured at destination.

Ø Control synchronizers-A double or multi flop synchronizer for domain crossing of single bit control signals.

CDC Elements

Ø Asynchronous clocks,synchronous /asynchronous resets,input port signals and their clock domains.

Ø Quasi static signals,qualifier signals,false cdc paths,case analaysis and the type of synchronizers .

Ø CDC constraints for design analysis:

Ø CDC constraints for placement:

Ø CDC constraints for design analysis:

Constraints to validate asynchronous crossing in RTL by performing structural & functional validation.

Need:

CDC analysis used to perform RTL code by performing structural & functional

Ø validation of CDC design :

To ensure that proper synchronization exists across clock domains to avoid metastability

problems.

To ensure data integrity is not compromised while crossing clock domains of different

frequency & validate that data coherency is maintained across clock domains.

CDC constraints for placement:

Time driven placement of synchronizer.

When constrained ,placement of data synchronizer register pair of the CDC logic would result in either a very large distance between their placement.

Or a interconnect with the large net delay makes the data crossing metastable.

To mitigate this,a”set_max_delay” constraint for those pairs of registers is set to be less than one clock cycle of destination clock with a fixed margin.

Design intent

• Goal:To capture design intent in a CDC constraints that would be used to validate asynchronous crossing logic both structurally and functionally in RTL prior to synthezing the design.

Step1:To capture all clocks and resets in the design.

For each subchip in the RTL design,list of clocks and resets as inferred by the CDC

analyser(EDA Vendor) tool is created.

After review,valid asynchronous clocks and valid asynchronous/synchronous

resets are included in the CDC constraints.

A structural CDC analysis is also run using the clock and reset definitions.

Problem

Step2:

When RTL design undergoes structural CDC analysis by a EDA vendor tool,get a list of synchronizing schemes identified by the tool to declare a domain crossing as valid.

Problem2:

• Not identifying a custom FIFO structure defined in the design & hence reporting crossing as invalid.In CDC constraint, custom FIFO can be defined to pass crossing as valid.

Problem3:

Even when the RTL design does not use a handshake protocol,some combination of signals passing through a double flop structure from one FSM clock domain to other FSM clock domain could structurally appear similar to a “request” and “acknowledge” signals to report a false positive domain crossing.

• For sub chips that donot use handshake protocol for domain crossing,checking for the REQ and ACK signals of a handshake has tp disabled during structural CDC analysis to avoid false positive reporting.

Qualifying data synchronizers in the design

Problem 4

• A signal that indicates when the data is stable to be sampled at destination domain is a qualifier signal that gates the domain crossing.

• When a valid qualifier is not used to pass the crossing or an invalid signal is used in place of a qualifier, then design intent has to be captured in the constraint.

Solution:

List of qualifiers used in structural CDC reporting would be reviewed to ensure that only signals with knowledge of when data would be stable for sampling of destination domain are used.

Example:A valid qualifier to be used in cdc constraints as

qualifier-name<>-from_clk<>_to_clk<>

Problem 5

Static flops such as config reg would flag CDC violations.

Solution5:By defining the names of such static signals in CDC constraints,false CDC violation due to static registers would not be flagged.

Example:quasi_static-name< net-name>

Delayed qualifier

Problem 6

In data synchronizer,reported 'qualifier signal' could be delayed through several registers before gating the domain crossing of the data bus.

Solution 6

Qulaifier identified by analysis tool may not be the valid gating signal and it could be the static signal to be declared as quasi_stable

false path

Problem7

Some paths exist but will never be crossed. A false violation flagged on such paths needs to be handled in CDC Constraints.

Solution 7

Define cdc false path at appropriate hierarchy level and would reduce CDC violations in the report

Example:cdc_false_path-from/-to/-through

could be used

Clock domain of input port signals of sub-chips in context with top level

Problem 8

Primary input ports of sub chips are associated with respective clock domains during the sub chip level CDC analysis(out of context with top level).

Once all sub chips are used to assemble a top level for CDC analysis, in context clock domains of the primary port of sub chips could be different from one defined at sub chip level CDC analysis.

CDC constraints for placement

Timing driven placement of double flop synchronizers.

Use Integrated syn(From library) for double flops used to syn single bit control signals which guarantees least amount of delay between sync flags to ensure that delay between F2 and F3 doesnot make signal metastability.

For all control signal syn with non integrated flops,

a max delay constraint set for their placement

a max delay set(10% to 20%) of one clock cycle of destination clock.

CDC METHODOLOGY

• More productive

Do with constraints than waivers.

Reduce waivers.

• Higher quality

Constraints gives design info that is not part of RTL that can be auto verified.

Automates a significant part of design review.

Convergence,jitter are almost impossible to do by inspect and are reliably done

using constraints and simulation.

Clock and reset set up check up

• Check setup correctness and completeness

• Important to fix all violations reported in this step to avoid false violations due to incorrect/incomplete setup.

Examples are as:

Ensure all flops are receiving a clock.

Ensure case analysis is defined preventing multiple clocks controlling some flop.

Ensure multiple clocks not defined on same clock path.

Periods,edge-list and domains are defined properly for clocks.

clock_reset_integrity goal

sanity check of clocks and resets.

clock and reset trees are properly designed and they are free of glitches ,races and other hazards.

If yoy do not have clock and reset definitions, must run the setup to define them before proceeding with verification.

cdc_verify_ goal

Verify all steps of cdc.

Metastability.

Coherency problem on reconvergent crossing.

Ensure all sync reset follow convention specied:reset_syn_style constraint.

Any change affects setup will be monitored.

If any setup issues(converging clocks ,missing clock definitions) will be reported.

Spyglass is an EDA tool for IC design, which can be used for Verilog code quality checking, power analysis and so on.

Verilog quality checks include lint and cdc checks. Lint is mainly used to check grammatical aspects, such as combinational logic, timing logic bitwidth matching, latch, lack of reset value in timing logic,... And so on.

Cdc detection is usually used to check whether the verilog code is correct across the clock. It extracts all the cross-clock paths and lists them according to the corresponding rules for users to determine item by item.

Spyglass cdc checks for constraints in xxx.sgdc format, indicating which signals are clocks, which are resets, and the clock domain of data-type signals.

1. Why write Sgdc constraints

Whether the spyglass tool matches or not can generate constraints file itself, we need to check the constraints file generated by the tool, and find out the omissions, modify the erroneous constraints, and supplement the missing constraints. The more detailed the Sgdc constraints, the less Error and warning the spyglass cdc reports, which can effectively reduce the workload.

3. Which signals need to be constrained by Sgdc

The input signals of the module indicate which signals are clocks, which are reset, and the clock domain of data signals.

Module output signal, no constraints

Both input and output signals of Black-box need to be constrained.

4. How to write Sgdc constraints

Define the current top-level: use current_design, as shown in the following figure: MAC is the current top-level, rmon_cnt is a black box within mac, only input and output definitions, there is no logic inside.

Define clokc for clock, reset for reset for reset, abstract for clock domain for data signal

5. Notes

Black box's input and output require constraints

In constraints, multi-bit signals cannot be replaced by [*], for example, tx_data [*] cannot be recognized, and tx_data[1023:0] must be written.

The bit-width representation of multi-bit data [xxx:xxx] cannot be computed, such as the incorrect expression of tx_data[1024-1:0]

current_design "mac"

clock -name "mac.host_clk" -domain host_clk -tag host_clk

clock -name "mac.sys_clk" -domain sys_clk -tag sys_clk

reset -name "mac.host_clk_soft_rst_n" -value 0

reset -name "mac.host_clk_hard_rst_n" -value 0

abstract_port -module mac -ports soc_wr -clock mac.host_clk

abstract_port -module mac -ports soc_rd -clock mac.host_clk

abstract_port -module mac -ports soc_rw_addr[12:0] -clock mac.host_clk

abstract_port -module mac -ports soc_wr_dat[31:0] -clock mac.host_clk

abstract_port -module mac -ports tx_data[1023:0] -clock mac.sys_clk

abstract_port -module mac -ports tx_eop -clock mac.sys_clk

abstract_port -module mac -ports tx_sop -clock mac.sys_clk

abstract_port -module mac -ports tx_vld -clock mac.sys_clk

#---------- rmon_cnt is the black box , only has input and output signal ,don't have logic in rmon_cnt.v " ------#

#### input signal ######

abstract_port -module rmon_cnt -ports mem_wr -clock mac.host_clk

abstract_port -module rmon_cnt -ports mem_rd -clock mac.host_clk

abstract_port -module rmon_cnt -ports mem_rw_addr[12:0] -clock mac.host_clk

abstract_port -module rmon_cnt -ports mem_wr_dat[31:0] -clock mac.host_clk

#### output signal ######

abstract_port -module rmon_cnt -ports mem_rd_datvld -clock mac.host_clk

abstract_port -module rmon_cnt -ports mem_rd_dat[31:0] -clock mac.host_clk

SpyGlass tool introduction

Currently includes: SpyGlass Lint, CDC, RDC, DFT ADV, Power. It is an important tool for RTL Signoff in the industry.

Some basic concepts of SpyGlass

1.Rule: It is the smallest unit of SpyGlass for RTL analysis.

2.Goal: It is a collection of related rules, combined to complete a specific task of RTL analysis. The user can use GuideWare-defined Goal, or according to the requirements of the project to select a series of rule sets to form a custom Goal. Point in the GUI Goal button to select the setting, of course, it can also be defined in the Prj file.

3.Sub-Methodology: It is a collection of related Goals, used to achieve a specific goal in a certain area, such as completing CDC check.

Currently includes SpyGlass CDC / Constraints / DFT / Power / TXV Methodology

4. Other terms that are not closely related to methodology:

SGDC : Constraint file, Mainly contains constraint information such as clock and reset.

Waiver : The file used to filter some results.

Severity : The report results are divided into four levels of information: Fatal, Error, Warning and INFO.

parameter: Some parameters can be set before RTL analysis, and some constraints are imposed on the inspection process

CDC

Assuming sender block uses clk1, while receiving block uses clk2. Sender block and receiving block use 4-phase REQ-ACK protocol for clock domain crossing.

Also assume the sender block interacts with its upstream logic using valid-ready protocol, and the receiving block interacts with its downstream logic using valid-ready protocol.

Obviously, 4-phase REQ-ACK protocol is slower than 2-phase REQ-ACK protocol, since each transfer involves 4 signal transitions compared to 2 signal transitions.

module Req_Ack_4phase_Sender

# ( parameter DWIDTH = 8)

(

input clk1,

input rst1_n, // assuming this reset is synchronized

input valid,

output logic ready,

input [DWIDTH-1:0] din,

output logic req,

input ack, // assuming this signal is synchronized from clk2 to clk1

output logic [DWIDTH-1:0] dout

);

always_ff @(posedge clk1 or negedge rst1_n)

if (~rst1_n)

req <= '0;

else if (valid & ready)

req <= '1;

else if (req & ack)

req <= '0;

always_ff @(posedge clk1 or negedge rst1_n)

if (~rst1_n)

ready <= '1;

else if (valid & ready) // this condition needs to be put first, otherwise same data may be sampled twice

ready <= '0;

else if (~req & ~ack)

ready <= '1;

always_ff @(posedge clk1)

if (valid & ready)

dout <= din;

endmodule

module Req_Ack_4phase_Receiver

# ( parameter DWIDTH = 8)

(

input clk2,

input rst2_n, // assuming this reset is synchronized

input ready,

output logic valid,

input [DWIDTH-1:0] din,

output logic ack,

input req, // assuming this signal is synchronized from clk1 to clk2

output logic [DWIDTH-1:0] dout

);

always_ff @(posedge clk2 or negedge rst2_n)

if (~rst2_n)

valid <= '0;

else if (valid & ready) // this condition needs to be put first, otherwise same data may be sent twice

valid <= '0;

else if (req & ~ack)

valid <= '1;

always_ff @(posedge clk2 or negedge rst2_n)

if (~rst2_n)

ack <= '0;

else if (valid & ready)

ack <= '1;

else if (~req & ack)

ack <= '0;

assign dout = din;

endmodule

The most common problem in the front-end design of CDC (Clock Domain Crossing) is that each asynchronous control signal and data signal must be properly handled in RTL, otherwise metastable state will occur, resulting in serious function false.

Introduction to SpyGlass CDC

Formal Check:

SpyGlass CDC tool is a kind of Formal Check MethodologyTool, compared to writing a case and running a simulation to find CDC problems, relying on SpgGlass can find CDC problems earlier, more comprehensively, and faster. It can:

Managing Multi-clock Designs

Systematic approach towards CDC problems

Check and report any unsynchronized signals: Clocks and Reset

Compared with Timing Check:

STA is not very good for async interface, only suitable for sync module analysis

CDC paths always need to be set to false paths

Generally it makes sense at the netlsit level later in the design

Compared with Functional Simulation:

Black box testing is hard to exhaust

White box testing requires some assertions

Need to cover all test branches of CDC

It is difficult to be lucky to cover all, generally only some problems can be found

Generally, problems are only found in the late stage of design

When SOC design involves too many clock domians, many third-party IPs are used, and the level of personnel involved is uneven, it is necessary to use SpyGlass CDC to check to ensure the quality of RTL.

In two different stages of the block-level and SOC integration of the project, the applicable CDC Goal is also different. Block-Level cares about the inside of the module, and only delivers after the module has no problems with the inspection. SOC integration mainly What is concerned is the CDC problem of the interface between the modules.