IC Design

 

Architectural level

 

At the architectural level, designer will make architectural decision to choose the clock frequency, micro-architecture of the design, how the design needs to be partitioned with respect to clock etc. In this phase, the designer will have lot of flexibility to reduce the overall power consumption.

 

The following are few major architectural low power techniques used.

 

•                      Clock Gating

•                      Architectural Clock Gating

•                      Dynamic Frequency Variation

 

Low power techniques come at a cost of Speed, Area, and Performance penalty. Based on the application or system requirement these techniques need to be carefully adopted. In a system, the significant portion of the dynamic power is consumed by the clock distribution network. Since, the clock buffers are having highest toggle rate in the system, these clock buffers can consume 50% or even more of the dynamic power. Further they will have high drive strength to reduce the clock delay. In addition, the flip-flops receiving the clock can dissipate dynamic power even though they are not switching states. We can turn off the clocks for the transistors or flip-flops when they are not functional which will help in reducing significant portion of dynamic power consumption, while preserving the state of the transistor or flipflops.

 

Existing clock gating methods

 

 

Gating based on inactive blocks/interfaces, protocol defined states

Architectural clock gating Implementation

Software programme entry and exit

Hardware driven and exit

Mixed hardware and software

 

 

Architectural Clock Gating

 

 

Architectural clock gating in the RTL is a configurable option in all versions of Cortex-M3.

In r1p1, it is controlled by several `defines, descriptions of which licensees of the RTL .

 

define CLOCKGATE
define INTEGRATION_CLOCKGATE
define ETM_CLOCKGATE
define CORE_CLOCKGATE

 In r2p0 it is controlled by the single CLKGATE_PRESENT parameter for each instantiation of the Cortex-M3, as described in the Cortex-M3 Integration and Implementation Manual available to RTL licensees.Control of the clock gating is inferred from the circuit activity.To minimize power consumption, ARM recommends the use of both architectural clock gating and leaf cell clock gating inferred by synthesis tools for ASIC (chip) implementation by RTL licensees. For FPGA prototyping, clock gating can cause some difficulty and inconvenience, and as the benefit is relatively small in FPGA prototypes, it makes sense to de-configure clock gating in this case

 

 The architectural Clock Gating is a context aware technique to determine functional idle period to optimize the power. While designing the architecture, the designer can identify the blocks for which clocks can be turned off under certain condition. These conditions need to be auto-detected by the RTL or programmed through the software and then, clocks can be turned off for that block thereby reducing significant amount of dynamic power.