Constraints

 

TIMING CONSTRAINTS

  

Start with no timing constraints

Use IDE to view the clock networks

Create basic clocks

Review Timing reports for coverage

Open synthesized design .See schematic

Report clock networks.Click constraints

See unconstrained

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 Before editing go for report_clocks

Edit timing constraints

 

Click generated clock

Description:

Create a generated clock object

 

Syntax:

create_generated_clock  [-name <arg>] [-source <args>] [-edges <args>]

                        [-divide_by <arg>] [-multiply_by <arg>]

                        [-combinational] [-duty_cycle <arg>] [-invert]

                        [-edge_shift <args>] [-add] [-master_clock <arg>]

                        [-quiet] [-verbose] <objects>

 

Returns:

new clock object

 

Usage:

  Name              Description

  -----------------------------

  [-name]           Generated clock name

  [-source]         Master clock source object pin/port

  [-edges]          Edge Specification

  [-divide_by]      Period division factor: Value >= 1

                    Default: 1

  [-multiply_by]    Period multiplication factor: Value >= 1

                    Default: 1

  [-combinational]  Create a divide_by 1 clock through combinational logic

  [-duty_cycle]     Duty cycle for period multiplication: Range: 0.0 to 100.0

                    Default: 0.0

  [-invert]         Invert the signal

  [-edge_shift]     Edge shift specification

  [-add]            Add to the existing clock in source_objects

  [-master_clock]   Use this clock if multiple clocks present at master pin

  [-quiet]          Ignore command errors

  [-verbose]        Suspend message limits during command execution

  <objects>         List of clock source ports, pins, or nets

 

Categories:

SDC, XDC

report_timing

if its ports go generic

if it is pins,do tcl for get_pins

and do report_timing  -from[get_pins     ..]-to[get_pins   ..]]

view contents of the report

Timing reports always start from primary clock propagate to the generated clocks and then on to the clock elements.

observe the  destination path clock timing.

See the requirements of the generated clock

See the destination  clock start of next clock edge and on to destination register

Slack is the required time – arrival time

Open the schematic of the netlist ,select clk_gen.window.zoom it

Observe the difference in schematic which is periodically enabled to generate the destination clocks.

In this case,generated clocks doesnot have the predefined relationship with the primary clocks clk pin

As a result,create a tcl command

create_generated clock

save the constraints

enter the tcl command report_clocks

observe the new generated clock included in the timing reports

click report timing summary

select new generated clk

see intraclk path,see the setup.double click any path to view the path properties

see the source clock path

source clock delay starts primary clock and propgate to generated clocks both automatically and manual generated clocks

see the destination clock path

starts from primary clock and propagated to generated clocks

close the properties.

 

Go to tools

report_timing –from[get_pins] –to[get_pins]

 

Datapath delay

 

Reg to reg

report_timing –from[all_registers] –to [all_registers]

see the slack in ns

report_timing –from[all_registers] –to [all_outputs]

see the slack in ns

report_timing –from[all_inputs] –to [all_registers]

see the slack in ns

 

See which is the highest slack in ns add min ns which can become as the he primary clock we need to choose it.

 

 

 

set input_delay

report_timing –from[all_inputs]

see the reports

set_input_delay –clock[get_clocks –phyclk0] –max3$my_input

report_timing –from$my_input –setup

see the reports

see the slack and input delay

insert the below tcl

set_input_delay –clock[get_clocks –phyclk0] –min1$my_input

report_timing –from$my_input –hold

report shows actual slack and the input delay

In addition see the edit timing constraint, can add set_input_delay

Input delay =highest slack obtained –all inputs  to all registers

 

set output_delay

report_timing –to[all_inputs]

see the reports

set_input_delay –clock[get clocks –sysclk0] $my_output

report_timing –from$my_input –hold

see the reports

see the actual slack and input delay

In addition see the edit timing constraint, can add set_output_delay

Output delay=highest slack obtained –all regsisters to all outputs

 

set clock groups

Open the synthesized design

Report clock interaction

Analyze the timing path from one clock domain to another clock domain

Report shows grid of clock interactions

Each grid is colored to indicate timing ,constraint status in inter clock path

If the two clock groups does not meet timing it is asynchronous

Clock frequencies are not integer multiples .Its impossible to find the relative fields between them.

 

report_clock_interactions –delay_type min_max –significant_digits 3 –name timing_1

see the wns and choose max

suppose if you have two constraints like clk_out1_clk_core, clk_out2_clk_core=>

 

join [get_timing_paths –from [get_clocks clk_out1_clk_core] –to[get_clocks clk_out2_clk_core]

-max_paths 200]

 

join [get_timing_paths –from [get_clocks clk_out2_clk_core] –to[get_clocks clk_out1_clk_core]

-max_paths 200]

 

Two clocks marked as asynchronous

Launch timing contraints-edit

Double click set clock_group

You need to specify two clock groups

Add the first clock group

Add the second by click + sign

Note asynchronous is chosen  by default.

Save the constarints

Report clock interactions

Observe the interclock path between clock grp1 and 2 is decalred blue confirming asynchronous 

Set false path

report timing_summary

See the interclock path

See the setup

set_false_path –from[get_pins   ]-to[get_pins ]]

report_timing –from [get_pins   ]-to[get_pins ]]

if sklack is infinite false path is sucessful

if not check the false path

 

set multicycle path

report_timing

See the interclock path

See the setup

 

 -hold

See the violated slack if any

See the requirement

You can see the change in slack