UVM

 

Q1: What is UVM? What is the advantage of UVM?

Ans: UVM (Universal Verification Methodology) is a standardized methodology for verifying the both complex & simple digital design in simple way.

UVM Features:

First methodology & second collection of class libraries for Automation

Reusability through testbench

Plug & Play of verification IPs

Generic Testbench Development

Vendor & Simulator Independent

Smart Testbench i.e. generate legal stimulus as from pre-planned coverage plan

Support CDV –Coverage Driven Verification

Support CRV –Constraint Random Verification

UVM standardized under the Accellera System Initiative

Register modeling

 

Q2: UVM derived from which language?

Ans: Here is the detailed connection between SV, UVM, OVM and other methodologies.

 

Q3. What is the difference between uvm_component and uvm_object?

                       OR

We already have uvm_object, why do we need uvm_component which is actually derived class of uvm_object?

Ans:

uvm_component:

Quasi Static Entity (after build phase it is available throughout the simulation)

Always tied to a given hardware(DUT Interface) Or a TLM port

Having phasing mechanism for control the behavior of simulation

Configuration Component Topology

 

uvm_object:

Dynamic Entity (create when needed, transfer from one component to other & then dereference)

Not tied to a given hardware or any TLM port

Not phasing mechanism

 

 

Q4: Why phasing is used? What are the different phases in uvm?

Ans: UVM Phases is used to control the behavior of simulation in a systematic way & execute in a sequential ordered to avoid race condition. This could also be done in system verilog but manually.

 

List of UVM Phases:

buid_phase

connect_phase

end_of_elaboration_phase

start_of_simulation_phase      

run _phase  (task)

Sub Phases of Reset Phase:

pre_reset_phase

reset_phase

post_reset_phase

pre_configure_phase

configure_phase

post_configure_phase

pre_main_phase

main_phase

post_main_phase

pre_shutdown_phase

shutdown_phase

post_shutdown_phase

extract_phase

check_phase

report_phase

Below figure makes it more clear

 

Q5: Which uvm phase is top - down , bottom – up & parallel?

Ans: Only build phase is a top-down & other phases are bottom-up except run phase which is parallel. The build phase works top-down since the testbench hierarchy may be configure so we need to build the branches before leafs

 

Q6: Why build phase is top – down & connect phase is bottom – up?

Ans: The connect phase is intended to be used for making TLM connections between components, which is why it occur after build phase. It work bottom-up so that its got the correct implementation all the way up the design hierarchy, if worked top-down this would be not possible

 

Q7: Which phase is function & which phase is task?

Ans: Only run phase is a task (time consuming phase) & other phases are functions (non-blocking)

 

Q8: How uvm phases initiate?

Ans: UVM phases initiate by calling run_test(“test1”) in top module. When run_test() method call, it first create the object of test top & then call all phases.

 

Q7: How test cases run from simulation command line?

Ans: In top module write run_test(); i.e. Don't give anything in argument.

Then in command line : +UVM_TESTNAME=testname

 

Q8: Difference between module & class based TB?

Ans: A module is a static object present always during of the simulation.

A Class is a dynamic object because they can come and go during the life time of simulation.

 

Q9: What is uvm_config_db ? What is difference between uvm_config_db & uvm_resource_db?

Ans: uvm_config_db is a parameterized class used for configuration of different type of parameter into the uvm database, So that it can be used by any component in the lower level of hierarchy.

uvm_config_db is a convenience layer built on top of uvm_resource_db, but that convenience is very important. In particular, uvm_resource_db uses a "last write wins" approach. The uvm_config_db, on the other hand, looks at where things are in the hierarchy up through end_of_elaboration, so "parent wins." Once you start start_of_simulation, the config_db becomes "last write wins."

All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator

It is extended from the uvm_resource_db#(T), so it is child class of uvm_resource_db#(T)

 

Q10:What is uvm_transaction, uvm_seq_item, uvm_object, uvm_component?

Q11:What is the advantage of  `uvm_component_utils() and `uvm_object_utils() ?

Q12:What is the difference between `uvm_do and `uvm_ran_send?

       diff between uvm_transaction and uvm_seq_item?

Q13:What is the difference between uvm _virtual_sequencer and uvm_sequencer ?

Q14:What are the benefits of using UVM?

Q15:What is super keyword? What is the need of calling super.build() and super.connect()?

Q16:Is uvm is independent of systemverilog ?

Q17:Can we have user defined phase in UVM?

Q18:What is p_sequencer ?

Q19:What is uvm RAL model ? why it is required ?

Q20:What is the difference between new() and create?

Q21:What is analysis port?

Q22:What is TLM FIFO?

Q23:How sequence starts?

Q24:What is the difference between UVM RAL model backdoor write/read and front door write/read ?

Q25:What is objection?

Q26:What is the advantage of `uvm_pre_body and `uvm_post_body ?

Q27:What is the difference between Active mode and Passive mode?

Q28:What is the difference between copy and clone?

Q29:What is UVM factory?

Q30:What are the types of sequencer? Explain each?

Q31:What are the different phases of uvm_component? Explain each?

Q32:How set_config_* works?

Q33:hat are the advantages of uvm RAL model ?

Q34:What is the different between set_config_* and uvm_config_db ?

Q35:What  are the different  override types?

Q36:What is virtual sequence and virtual sequencer?

Q37:Explain end of simulation in UVM?

Q38:How to declare multiple imports?

Q39:What is symbolic representation of port, export and analysis port?

Q40:What is the difference in usage of $finish and global stop request in UVM?

Q41:Why we need to register class with uvm factory?

Q42:can we use set_config and get_config in sequence ?

Q43:What is uvm_heartbeat ?

Q44:how to access DUT signal in uvm_component/uvm_object ?