Engineering Change Order

 Engineering Change Order (ECO) is the process of making local changes to the design netlist without re-running the entire synthesis and P&R from scratch.

• ECO Types:

 • Functional ECO

• Change the functionality of the design

• Non-functional ECO:

• Fix timing, cross talk

• Stage:

• Pre-masks

• Usage of standard cells to implement the modifications

• Post-masks

• Base layer taped-out, metal fix using spare cells

As with other types of formal analysis, equivalence checking of a large design is a tough mathematical problem. For most ASICs and simple FPGAs, the problem can be simplified by mapping the state elements (memory and registers) between the two designs. If this is possible, combinational equivalence checking needs to consider only the combinational logic between the state elements.

Sequential equivalence checking, in its purest form, treats two designs as black boxes in which the input and outputs must match but the internal state can be entirely different.

 In practice, two designs may be similar but not close enough for combinational equivalence checking. This is commonly the case for FPGA synthesis, which may reorder state machines or migrate logic across registers to meet timing requirements. Thus, proving formal equivalence for FPGAs typically employs sequential checking for optimized parts of the design and combinational checking for the remainder.