SoC Integration

 

Define the architecture functions

 Define subsystem logic components to support arch functions

 Provide interfaces between logic components of sub system

 Do packaging of subsystem to provide Integrated SoC

 Validate SoC with integrated sub system

Define subsystem components

Instances

Subsystem connectivity

 Inputs

Design files

 Intent command files

 Interactively entered design intent

 Tech files with documentation files

 Verification files

 Interface definition

 Optional files

 Package information

Load the design

Design configuration intent

Memory map definition

Test regression environment

Outputs: Batch script and design constraints

 Synthesis- specify reference technology,specify clocks,specify synthesis,test methodology and specify timing exception,specify port constraint and verify intent.In the synthesis do the below:

For clocks –real clock,virtual clock,generated clock

 Define port constraints

 Define Timing exceptions

 set_false_path

set_multi_cycle_path

set_max_delay

set_min_delay

reset_path

set_disable_timing

Declare Power intent-by UPF/CPF

Memory maps -address bank, address block,register, register field

Defining interface and packaging into each component :-

To build Subsystem;

 Automatically connects interfaces of components to each other;

 Manually connects and disconnect ports as needs;

Generate top level for subsystem;

Configure each components in subsystem;

Export interface to top level of subsystem for connection of next level design.

The design flow includes steps for implementation, integration, and programming. The processes must be completed before the processor is ready for operation.The processor is delivered as synthesizable RTL. Before it can be used in a product, it must go through the following process:

 Implementation, Integration, Programming

 Implementation: The implementer configures the RTL and may synthesize it to produce a hard macrocell or may synthesize the whole design after implementation.

 Integration      :The integrator connects the implemented design into a SoC. This includes connecting it to a memory system and peripherals.

 Programming: System programmer develops the software required to configure and initialize the processor and tests the required application software. Each stage in the process can be performed by a different party. Implementation and integration choices affect the behavior and features of the processor.

 For MCUs, often a single design team integrates the processor before synthesizing the complete design. Alternatively, the team can synthesize the processor on its own or partially integrated, to produce a macrocell that is then integrated, possibly by a separate team. The operation of the final device depends on: Build configuration, Configuration inputs, Software configuration.

 Build configuration: Implementer chooses the options that affect how the RTL source files are pre-processed. These options usually include or exclude logic that affects one or more of the area, maximum frequency, and features of the resulting macrocell.

 Configuration inputs: The integrator configures some features of the processor by tying inputs to specific values. These configurations affect the start-up behavior before any software configuration is made. They can also limit the options available to the software.

 Software configuration: The programmer configures the processor by programming particular values into registers. This affects the behavior of the processor.

 For SoC/ASIC designs, the ADC and DAC IP need to be sourced from specialist IP providers. We need to know the Clock sources, multiple power domains. Modern SoC/ASICs that run at over 100MHz, many ATE might not be able to support at-speed testing at such a high clock speed and in those cases, traditional functional tests might be more suitable. In SoC/ASIC designs, have the following clock sources- External crystal oscillator, Internal RC oscillator for medium speed.

 1. Logical and functional errors

 2. Clocking issues

 3. Analog–digital interfaces

4. Crosstalk

5. Power management

6. Analog circuits

7. Yield/reliability

8. Timing

9. Firmware

10. IR drop